SCAN90CP02SPX National Semiconductor, SCAN90CP02SPX Datasheet - Page 7

• Manufacturer Part Number: SCAN90CP02SPX
• Manufacturer: National Semiconductor

Specifications of SCAN90CP02SPX

• Array Configuration: 2x2
• Number Of Arrays: 1
• Differential Data Transmission: Yes
• Power Supply Requirement: Single
• Operating Supply Voltage (typ): 3.3V
• Package Type: LLP EP
• Pin Count: 28
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Cascading Capability: No
• On-chip Buffers: No
• On-chip Decoder: No
• On-chip Latch Circuit: No
• On-chip Mux/demux: No
• Programmable: No
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Output Level: LVDS
• Lead Free Status / RoHS Status: Not Compliant

Symbol
f
t
t
t
t
t
t
t
MAX
S
H
S
H
W
W
REC
SCAN Circuitry Timing Requirements
Note 3: “Absolute Maximum Ratings” are the ratings beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits.
Note 4: Typical parameters are measured at V
Note 5: Differential output voltage V
Note 6: Output offset voltage V
Note 7: Jitter is not production tested, but guaranteed through characterization on a sample basis.
Note 8: Random Jitter, or RJ, is measured RMS with a histogram including 1500 histogram window hits. The input voltage = V
750MHz, t
Note 9: Deterministic Jitter, or DJ, is measured to a histogram mean with a sample size of 350 hits. The input voltage = V
t
Note 10: Total Jitter, or TJ, is measured peak to peak with a histogram including 3500 window hits. Stimulus and fixture jitter has been subtracted. The input
voltage = V
Timing Diagrams
r
= t
f
= 50ps (20% to 80%). The K28.5 pattern is repeating bit streams of (0011111010 1100000101).
r
ID
= t
= 500mV, 2
f
Parameter
Maximum TCK Clock Frequency
TDI to TCK, H or L
TDI to TCK, H or L
TMS to TCK, H or L
TMS to TCK, H or L
TCK Pulse Width, H or L
TRST Pulse Width, L
Recovery Time, TRST to TCK
= 50ps (20% to 80%).
23
-1 PRBS pattern at 1.5 Gbps, t
OS
is defined as the average of the LVDS single-ended output voltages at logic high and logic low states.
OD
is defined as ABS(OUT+–OUT−). Differential input voltage V
DD
= 3.3V, T
r
= t
A
= 25°C. They are for reference purposes, and are not production-tested.
f
= 50ps (20% to 80%).
FIGURE 3. LVDS Signals
Conditions
R
C
L
L
= 500Ω,
= 35 pF
7
ID
is defined as ABS(IN+–IN−).
25.0
10.0
Min
1.0
2.0
2.0
1.5
2.5
2.0
20071415
ID
Typ
= 500mV, K28.5 pattern at 1.5 Gbps,
ID
= 500mV, 50% duty cycle at
Max
www.national.com
Units
MHz
ns
ns
ns
ns
ns
ns
ns