MM58274CN-12 National Semiconductor, MM58274CN-12 Datasheet - Page 8

• Manufacturer Part Number: MM58274CN-12
• Manufacturer: National Semiconductor

Specifications of MM58274CN-12

• Bus Type: Parallel
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 16
• Mounting: Through Hole
• Date Format: DW:DM:M:Y
• Time Format: HH:MM:SS:hh
• Lead Free Status / RoHS Status: Not Compliant

Functional Description
Control Register
There are three registers which control different operations
of the clock
a) the clock setting register
b) the interrupt register
c) the control register
The clock setting and interrupt registers both reside at ad-
dress 15 access to one or the other being controlled by the
interrupt select bit data bit 1 of the control register
The clock setting register programs the timekeeping of the
clock The 12-hour mode and the AM PM indicator occupy
bits 0 and 1 respectively Data bits 2 and 3 set the leap year
counter
The interrupt register controls the operation of the interrupt
timer selecting the required delay period and either single
or repeated interrupt
The control register is responsible for controlling the opera-
tions of the clock and supplying status information to the
processor It appears as two different registers one with
write only access and one with read only access
The write only register consists of a bank of four latches
which control the internal processes of the clock
The read only register contains two output data latches
which will supply status information for the processor Table
III shows the mapping of the various control latches and
status flags in the control register The control register is
located at address 0
The write only portion of the control register contains four
latches
A logic 1 written into the test bit puts the device into test
mode This allows setting of the oscillator frequency as well
as rapid testing of the device registers if required A more
complete description is given in the Test Mode section For
normal operation the test bit is loaded with logic 0
The clock start stop bit stops the timekeeping of the clock
and resets to 0 the tenths of seconds counter The time of
day may then be written into the various clock registers and
the clock restarted synchronously with an external time
source Timekeeping is maintained thereafter
A logic 1 written to the start stop bit halts clock timing Tim-
ing is restarted when the start stop bit is written with a logic
0
The interrupt select bit determines which of the two regis-
ters mapped onto address 15 will be accessed when this
address is selected
Access (addr0)
Read From
Write To
Data-Changed Flag
1
0
e
e
Test Mode
DB3
Test
Normal
(Continued)
TABLE III The Control Register Layout
Clock Start Stop
1
0
e
e
Clock Stop
Clock Run
DB2
0
8
A logic 0 in the interrupt select bit makes the clock setting
register available to the processor A logic 1 selects the
interrupt register
The interrupt start stop bit controls the running of the inter-
rupt timer It is programmed in the same way as the clock
start stop bit logic 1 to halt the interrupt and reset the tim-
er logic 0 to start interrupt timing
When no interrupt is programmed (interrupt control register
set to 0) the interrupt start stop bit is automatically set to a
logic 1 When any new interrupt is subsequently pro-
grammed timing will not commence until the start stop bit
is loaded with 0
In the single interrupt mode interrupt timing stops when a
timeout occurs The processor restarts timing by writing log-
ic 0 into the start stop bit
In repeated interrupt mode the interrupt timer continues to
count with no intervention by the processor necessary
Interrupt timing may be stopped in either mode by writing a
logic 1 into the interrupt start stop bit The timer is reset and
can be restarted in the normal way giving a full time delay
period before the next interrupt
In general the control register is set up such that writing 0’s
into it will start anything that is stopped pull the clock out of
test mode and select the clock setting register onto the bus
In other words writing 0 will maintain normal clock operation
and restart interrupt timing etc
The read only portion of the control register has two status
outputs
Since the MM58274C-12 keeps real time the time data
changes asynchronously with the processor and this may
occur while the processor is reading time data out of the
clock
Some method of warning the processor when the time data
has changed must thus be included This is provided for by
the data-changed flag located in bit 3 of the control register
This flag is set by the clock setting pulse which also clocks
the time registers Testing this bit can tell the processor
whether or not the time has changed The flag is cleared by
a read of the control register but not by any write operations
No other register read has any effect on the state of the
data-changed flag
Data bit 0 is the interrupt flag This flag is set whenever the
interrupt timer times out pulling the interrupt output low In a
polled interrupt routine the processor can test this flag to
determine if the MM58274C-12 was the interrupting device
This interrupt flag and the interrupt output are both cleared
by a read of the control register
0
e
1
e
Clock Setting Register
Interrupt Select
Interrupt Register
DB1
0
Interrupt Start Stop
1
0
e
e
Interrupt Flag
Interrupt Stop
Interrupt Run
DB0