MM58274CN-12 National Semiconductor, MM58274CN-12 Datasheet - Page 13

• Manufacturer Part Number: MM58274CN-12
• Manufacturer: National Semiconductor

Specifications of MM58274CN-12

• Bus Type: Parallel
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 16
• Mounting: Through Hole
• Date Format: DW:DM:M:Y
• Time Format: HH:MM:SS:hh
• Lead Free Status / RoHS Status: Not Compliant

Functional Description
APPLICATION HINTS
Time Reading Using Interrupt
In systems such as point of sale terminals and data loggers
time reading is usually only required on a random demand
basis Using the data-changed flag as outlined in the section
on methods of operation is ideal for this type of system
Some systems however need to sense a change in real
time e g
clocks any system where real time is displayed
The interrupt timer on the MM58274C-12 can generate in-
terrupts synchronously with the time registers changing us-
ing software to provide the initial synchronization
In single interrupt mode the processor is responsible for ini-
tiating each timing cycle and the timed period is accurate to
In repeated interrupt mode the period from the initial proces-
sor start to the first timeout is also only accurate to
The following interrupts maintain accurate delay periods rel-
ative to the first timeout Thus to utilize interrupt to control
time reading we will use repeated interrupt mode
In repeated mode the time period between interrupts is ex-
act which means that timeouts will always occur at the
same point relative to the internal clock setting pulses The
case for 0 1s interrupts is shown in Figure A-1 The same is
true for other delay periods only there will be more clock
setting pulses between each interrupt timeout If we set up
the interrupt timer so that interrupt always times out just
after the clock setting pulse occurs ( Figure A-2 ) then there
is no need to test the data-changed flag as we know that
the time data has just changed and will not alter again for
another 100 ms
This can be achieved as outlined below
1) Follow steps 1 and 2 of the section on interrupt program-
ming In step 2 set up for repeated interrupt
g
1 ms
industrial timers process controllers TV VCR
FIGURE A-1 Time Delay from Clock Setting Pulses to Interrupt is Constant
FIGURE A-2 Interrupt Timer Synchronized with Clock Setting Pulses
(Continued)
g
1 ms
13
the data-changed flag
tween read strobes (i e between reading tens of minutes
2) Read control register AD0 This is a dummy read to reset
3) Read control register AD0 until data-changed flag is set
4) Write 0 or 2 to control register Interrupt timing com-
mences
Time Reading with Very Slow Read Cycles
If a system takes longer than 100 ms to complete reading of
all the necessary time registers (e g when CMOS proces-
sors are used) or where high level interpreted language rou-
tines are used then the data-changed flag will always be set
when tested and is of no value In this case the time regis-
ters themselves must be tested to ensure data accuracy
The technique below will detect both time changing be-
and units of hours) and also time changing during read
which can produce invalid data
1) Read and store the value of the lowest order time register
required
2) Read out all the time registers required The registers
may be read out in any order simplifying software require-
ments
3) Read the lowest order register and compare it with the
value stored previously in step 1 If it is still the same then
all time data is good If it has changed then store the new
value and go back to step 2
In general the rule is that the first and last reads must both
be of the lowest order time register These two values can
then be compared to ensure that no change has occurred
This technique works because for any higher order time reg-
ister to change all the lower order registers must also
change If the lowest order register does not change then
no higher order register has changed either
TL F 5602 – 12
TL F 5602– 11