1338-31DCGI8 IDT, Integrated Device Technology Inc, 1338-31DCGI8 Datasheet - Page 7

• Manufacturer Part Number: 1338-31DCGI8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 1338-31DCGI8

• Bus Type: Serial (I2C)
• User Ram: 56Byte
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 8
• Mounting: Surface Mount
• Date Format: DW:DM:M:Y
• Time Format: HH:MM:SS
• Lead Free Status / RoHS Status: Compliant

being PM. In the 24-hour mode, bit 5 is the second 10-hour
bit (20–23 hours). If the 12/24-hour mode select is changed,
the hours register must be re-initialized to the new format.
On an I
set of registers. The time information is read from these
secondary registers, while the clock continues to run. This
eliminates the need to re-read the registers in case of an
update of the main registers during a read.
Table 4. Control Register (07H)
Table 5. Square Wave Output
IDT® REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 7
IDT1338
REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM
Name
OUT
Bit #
POR
X
X
X
X
0
1
2
C START, the current time is transferred to a second
The control register controls the operation of the SQW/OUT pin and provides oscillator status.
Bit 7: Output Control (OUT). Controls the output level of the SQW/OUT pin when the square-wave output is disabled. If SQWE
= 0, the logic level on the SQW/OUT pin is 1 if OUT = 1; it is 0 if OUT = 0.
Bit 5: Oscillator Stop Flag (OSF). A logic 1 in this bit indicates that the oscillator has stopped or was stopped for some time
period and can be used to judge the validity of the clock and calendar data. This bit is edge triggered, and is set to logic 1 when
the internal circuitry senses the oscillator has transitioned from a normal run state to a STOP condition. The following are
examples of conditions that may cause the OSF bit to be set:
1) The first time power is applied.
2) The voltage present on VCC and VBAT are insufficient to support oscillation.
3) The CH bit is set to 1, disabling the oscillator.
4) External influences on the crystal (i.e., noise, leakage, etc.).
This bit remains at logic 1 until written to logic 0. This bit can only be written to logic 0. Attempting to write OSF to logic 1 leaves
the value unchanged.
Bit 4: Square-Wave Enable (SQWE). When set to logic 1, this bit enables the oscillator output to operate with either VCC or
V
Bits 1 and 0: Rate Select (RS1 and RS0). These bits control the frequency of the square-wave output when the square-wave
output has been enabled. The table below lists the square-wave frequencies that can be selected with the RS bits.
BAT
RS1
applied. The frequency of the square-wave output depends upon the value of the RS0 and RS1 bits.
Bit 7
0
0
1
1
X
X
OUT
1
RS0
0
1
0
1
X
X
Bit 6
0
0
SQW Output
32.768 kHz
4.096 kHz
8.192 kHz
Bit 5
OSF
1 Hz
1
0
1
SQWE
Bit 4
1
SQWE
1
1
1
1
0
0
Bit 3
0
0
Bit 2
0
0
Bit 1
RS1
1
Bit 0
RS0
1
IDT1338
REV K 032910
RTC