ICS8536AGI-33T IDT, Integrated Device Technology Inc, ICS8536AGI-33T Datasheet
ICS8536AGI-33T
Specifications of ICS8536AGI-33T
Related parts for ICS8536AGI-33T
ICS8536AGI-33T Summary of contents
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Integrated Circuit Systems, Inc ENERAL ESCRIPTION The ICS8536I- low skew, high perfor mance 1-to-6 Crystal Oscillator/LVCMOS-to- HiPerClockS™ 3.3V LVPECL/LVCMOS fanout buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from ...
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Integrated Circuit Systems, Inc ABLE IN ESCRIPTIONS ...
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Integrated Circuit Systems, Inc ABLE ONTROL NPUT UNCTION ...
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Integrated Circuit Systems, Inc BSOLUTE AXIMUM ATINGS Supply Voltage, V 4.6V CC Inputs, V (LVCMOS) -0. Outputs, V (LVCMOS) -0. Inputs, V (LVPECL) -0. Outputs, I (LVPECL) O ...
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Integrated Circuit Systems, Inc. T 4C. LVCMOS / LVTTL DC C ABLE HARACTERISTICS ...
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Integrated Circuit Systems, Inc. T 6A. LVPECL AC C ABLE HARACTERISTICS ...
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Integrated Circuit Systems, Inc. P ARAMETER 2V V CC, V CCO_LVPECL LVPECL V EE -1.3V ± 0.165V 3.3V LVPECL UTPUT OAD EST V CC CLK 2 nQ0:nQ2 Q0: LVPECL P D ROPAGATION ELAY nQx ...
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Integrated Circuit Systems, Inc. nQ0:nQ2 Q0: PERIOD t PW odc = t PERIOD LVPECL UTPUT UTY YCLE ULSE 80% Clock 20% Outputs t R LVPECL UTPUT ISE ALL ...
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Integrated Circuit Systems, Inc ECOMMENDATIONS FOR NUSED I : NPUTS RYSTAL NPUT For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, ...
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Integrated Circuit Systems, Inc. T LVPECL O ERMINATION FOR UTPUTS The clock layout topology shown below is a typical termi- nation for LVPECL outputs. The two different layouts men- tioned are recommended only as guidelines. FOUT and nFOUT are low ...
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Integrated Circuit Systems, Inc. This section provides information on power dissipation and junction temperature for the ICS8536I-33. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8536I-33 is the sum of the core ...
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Integrated Circuit Systems, Inc. 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 4. F IGURE T o calculate worst case ...
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Integrated Circuit Systems, Inc ABLE VS IR LOW ABLE FOR JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The ...
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Integrated Circuit Systems, Inc ACKAGE UTLINE UFFIX FOR T ABLE Reference Document: JEDEC Publication 95, MO-153 8536AGI-33 PRELIMINARY LVCMOS- -3.3V LVPECL/LVCMOS F TO TSSOP EAD ACKAGE IMENSIONS ...
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Integrated Circuit Systems, Inc ABLE RDERING NFORMATION ...