PCK2001RDB NXP Semiconductors, PCK2001RDB Datasheet - Page 8

• Manufacturer Part Number: PCK2001RDB
• Description: Clock Buffer 14.318-150 MHZ 12C 1:6 CK BUFR
• Manufacturer: NXP Semiconductors

Specifications of PCK2001RDB

• Number Of Outputs: 6
• Operating Supply Voltage (max): 3.465V
• Operating Temp Range: 0C to 70C
• Propagation Delay Time: 3.5ns
• Operating Supply Voltage (min): 3.135V
• Mounting: Surface Mount
• Pin Count: 16
• Operating Supply Voltage (typ): 3.3V
• Package Type: SSOP
• Quiescent Current: 100uA
• Power Dissipation: 850mW
• Input Frequency: 533MHz
• Duty Cycle: 55%
• Operating Temperature Classification: Commercial
• Max Input Freq: 533 MHz
• Propagation Delay (max): 2.6 ns
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Maximum Power Dissipation: 850 mW
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-16
• Lead Free Status / RoHS Status: Compliant
• Other names: PCK2001RDB,112

Philips Semiconductors
SERIAL CONFIGURATION MAP
The serial bits will be read by the clock buffer in the following order:
All unused register bits (Reserved and N/A) should be desined as “Don’t Care”. It is expected that the controller will force all of these bits to a
“0” level.
All register bits labeled “Initialize to 0” must be written to zero during intialization. Failure to do so may result in a higher than normal operating
current. The controller will read back the last written value.
Byte 0: Active/inactive register
1 = enable; 0 = disable
NOTE:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are
Byte 1: Active/inactive register
1 = enable; 0 = disable
NOTE:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are
Byte 2: Active/inactive register
NOTE:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are
2002 Dec 13
533 MHz I
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 2 - Bits 7, 6, 5, 4, 3, 2, 1, 0
not expected to be configured during the normal modes of operation.
not expected to be configured during the normal modes of operation.
not expected to be configured during the normal modes of operation.
BIT
BIT
BIT
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
PIN#
PIN#
PIN#
2
15
13
—
—
—
—
—
—
—
—
—
—
—
11
—
—
—
—
—
—
—
6
3
1
C 1:6 clock buffer
BUF_OUT14
BUF_OUT11
BUF_OUT17
BUF_OUT7
BUF_OUT2
BUF_OUT0
NAME
NAME
NAME
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
8
DESCRIPTION
DESCRIPTION
DESCRIPTION
Active/Inactive
Active/Inactive
Active/Inactive
Active/Inactive
Active/Inactive
Active/Inactive
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PCK2001R
Product data