CY2DP3110AI Cypress Semiconductor Corp, CY2DP3110AI Datasheet - Page 2

• Manufacturer Part Number: CY2DP3110AI
• Manufacturer: Cypress Semiconductor Corp
• Type: Clock Driverr

Specifications of CY2DP3110AI

• Number Of Clock Inputs: 2
• Mode Of Operation: Differential
• Output Frequency: 1500MHz
• Output Logic Level: ECL/PECL
• Operating Supply Voltage (min): -2.375/2.375V
• Operating Supply Voltage (typ): -2.5/-3.3/2.5/3.3V
• Operating Supply Voltage (max): -3.465/3.465V
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Signal Type: ECL/HSTL/PECL
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-07469 Rev. *I
Pin Definitions
Table 1.
Governing Agencies
The following agencies provide specifications that apply to the
CY2DP3110. The agency name and relevant specification is
listed below in Table 2.
Table 2.
2
3
4
5
6
7
8
1,9,16,
25,32
31,29,27,24,22,20,18,
15,13,11
30,28,26,23,21,19,17,
14,12,10
JEDEC
Mil-Spec
Notes:
1. In the I/O column, the following notation is used: I for Input, O for Output, PD for Pull-Down, PU for Pull-Up, and PWR for Power.
2. In ECL mode (negative power supply mode), V
3. V
V
and are between V
CLK_SEL
EE
BB
Control
Agency Name
is available for use for single-ended bias mode for |3.3V| supplies (not |2.5V|).
is connected to GND (0V) and V
0
1
Pin
CC
CLKA, CLKA# input pair is active (Default condition with no connection to pin)
CLKA can be driven with ECL- or PECL-compatible signals with respective power configurations
CLKB, CLKB# input pair is active.
CLKB can be driven with HSTL compatible signals with respective power configurations
[1, 2, 3]
and V
EE
JESD 020B (MSL)
JESD 8-6 (HSTL)
JESD 51 (Theta JA)
JESD 8–2 (ECL)
JESD 65–B (skew,jitter)
883E Method 1012.1 (Thermal Theta JC)
CLK_SEL
.
Q#(0:9)
CLKA#
CLKB#
CLKB,
Q(0:9)
Name
CLKA
VCC
VBB
VEE
CC
is either +3.3V or +2.5V. In both modes, the input and output levels are referenced to the most positive supply (V
I,PD/PU ECL/PECL Differential Input Clocks.
I,PD/PU
I,PD
–PWR
+PWR
EE
I,PD
I,PD
I/O
Specification
O
O
O
is either –3.3V or –2.5V and V
[1]
ECL/PECL Input Clock Select.
ECL/PECL Differential Input Clocks.
ECL/PECL ECL/PECL Differential Output Clocks.
ECL/PECL ECL/PECL Differential Output Clocks.
Power
Power
HSTL
HSTL
Type
Bias
Reference Voltage Output.
Alternate Differential Input Clocks.
Alternate Differential Input Clocks.
Negative Power Supply.
Positive Power Supply.
CC
Operation
is connected to GND (0V). In PECL mode (positive power supply mode),
Description
FastEdge™ Series
CY2DP3110
Page 2 of 10
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