889875AKLF IDT, Integrated Device Technology Inc, 889875AKLF Datasheet - Page 8

• Manufacturer Part Number: 889875AKLF
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Dividerr

Specifications of 889875AKLF

• Number Of Clock Inputs: 1
• Mode Of Operation: Differential
• Output Frequency: >2000MHz
• Output Logic Level: LVDS
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (max): 2.625V
• Package Type: VFQFN
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Signal Type: CML/LVDS/LVPECL
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Compliant

Application Information
Wiring the Differential Input to Accept Single Ended Levels
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and V
R2/R1 = 0.609.
Recommendations for Unused Input Pins
Inputs:
LVCMOS Select Pins
All control pins have internal pull-ups; additional resistance is not
required but can be added for additional protection. A 1kΩ resistor
can be used.
IDT™ / ICS™ LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
ICS889875
DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
DD
= 3.3V, V_REF should be 1.25V and
DD
/2 is
8
Figure 2. Single-Ended Signal Driving Differential Input
O
LVDS Outputs
All unused LVDS output pairs can be either left floating or
terminated with 100Ω across. If they are left floating, we
recommend that there is no trace attached.
UT
puts:
Single Ended Clock Input
C1
0.1u
ICS889875AK REV. B OCTOBER 27, 2008
V_REF
R1
1K
R2
1K
V
DD
IN
nIN