A6810SLWTR-T Allegro, A6810SLWTR-T Datasheet - Page 8

no-image

A6810SLWTR-T

Manufacturer Part Number
A6810SLWTR-T
Description
VFD DRVR 7V/60V 15mA 20-Pin SOIC W T/R
Manufacturer
Allegro
Datasheet

Specifications of A6810SLWTR-T

Package
20SOIC W
Driver Type
VFD
Maximum Output Current
15 mA
Maximum Operating Supply Voltage
7|60 V
A6810
20X
0.10
0.41 ±0.10
C
20
For Reference Only
Dimensions in millimeters
(Reference JEDEC MS-013 AC)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
1
1.52
2
A
+0.25
–0.38
A
12.80±0.20
18
1
10-Bit Serial Input Latched Source Driver
2
0.46 ±0.12
1.27
22.86 ±0.51
Package LW 20-Pin SOICW
Package A 18-Pin DIP
7.50±0.10
2.54
0.20 ±0.10
SEATING
PLANE
2.65 MAX
10.30±0.33
5.33 MAX
6.35
3.30
+0.76
–0.25
+0.51
–0.38
C
SEATING
PLANE
A Terminal #1 mark area
All dimensions nominal, not for tooling use
(reference JEDEC MS-001 AC)
Dimensions in inches
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
10.92
A Terminal #1 mark area
B
+0.38
–0.25
C
Reference pad layout (reference IPC SOIC127P1030X265-20M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
GAUGE PLANE
4° ±4
0.25
0.84
SEATING PLANE
0.27
+0.44
–0.43
+0.07
–0.06
2.25
7.62
0.25
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
20
1
+0.10
–0.05
2
B
PCB Layout Reference View
0.65
1.27
9.50
7

Related parts for A6810SLWTR-T