A6810SLWTR-T Allegro, A6810SLWTR-T Datasheet
A6810SLWTR-T
Specifications of A6810SLWTR-T
Related parts for A6810SLWTR-T
A6810SLWTR-T Summary of contents
Page 1
... NOTE: For detailed information on purchasing options, contact your local Allegro field applications engineer or sales representative. Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no respon- sibility for its use ...
Page 2
Serial Input Latched Source Driver Features and Benefits ▪ Controlled output slew rate ▪ High-speed data storage ▪ minimum output breakdown ▪ High data-input rate ▪ PNP active pull-downs ▪ Low output-saturation voltages ▪ Low-power CMOS logic ...
Page 3
... Yes A6810KLWTR-T Yes A6810SLWTR-T Yes *Variant is in production but has been determined to be LAST TIME BUY. This classification indicates that the variant is obsolete and notice has been given. Sale of the variant is currently restricted to existing customer applications. The variant should not be purchased for new design applications because of obsolescence in the near future ...
Page 4
... Serial Input Latched Source Driver A6810 Thermal Characteristics Characteristic Package Thermal Resistance *Additional thermal information available on the Allegro website. Pin-out Diagrams Symbol Test Conditions* Package A, 1-layer PCB with copper limited to solder pads R θJA Package LW, 1-layer PCB with copper limited to solder pads ...
Page 5
... Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com = 5 V Max. Units -15 μA — V 1.5 V — mA — V 1.7 V 1.0 μA μA -1 ...
Page 6
... BLANKING input. With the BLANK ING input low, the outputs are con trolled by the state of their re spec tive latches. DATA t p(STH-QH) 90% DATA 10% Dwg. WP-029 t dis(BQ 90% 50% DATA 10% Dwg. WP-030A Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 ...
Page 7
... L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State TRUTH TABLE Serial Latch Contents Data Strobe I Output Input N-1 N N-1 N Output Con tents ... I I Blanklng N ... R R N-1 N ... N ... Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com ... I I N-1 N ... P P N-1 N ... ...
Page 8
... SEATING PLANE GAUGE PLANE Reference pad layout (reference IPC SOIC127P1030X265-20M) All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9.50 1 ...
Page 9
... The in for ma tion in clud ed herein is believed rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. ...