MT48LC4M16A2TG-75 IT:G Micron Technology Inc, MT48LC4M16A2TG-75 IT:G Datasheet - Page 25
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MT48LC4M16A2TG-75 IT:G
Manufacturer Part Number
MT48LC4M16A2TG-75 IT:G
Description
DRAM Chip SDRAM 64M-Bit 4Mx16 3.3V 54-Pin TSOP-II Tray
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC4M16A2TG-75_ITG.pdf
(72 pages)
Specifications of MT48LC4M16A2TG-75 IT:G
Density
64 Mb
Maximum Clock Rate
133 MHz
Package
54TSOP-II
Address Bus Width
14 Bit
Operating Supply Voltage
3.3 V
Maximum Random Access Time
6|5.4 ns
Operating Temperature
-40 to 85 °C
Organization
4Mx16
Address Bus
14b
Access Time (max)
6/5.4ns
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
140mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Not Compliant
Figure 12:
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
64MSDRAM_2.fm - Rev. N 12/08 EN
Consecutive READ Bursts
Note:
COMMAND
COMMAND
ADDRESS
ADDRESS
Each READ command may be to any bank. DQM is LOW.
CLK
CLK
DQ
DQ
T0
T0
BANK,
COL n
BANK,
READ
COL n
READ
CAS Latency = 2
CAS Latency = 3
T1
T1
NOP
NOP
25
T2
T2
NOP
NOP
D
OUT
n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3
T3
NOP
NOP
D
n + 1
D
OUT
OUT
n
TRANSITIONING DATA
T4
T4
BANK,
BANK,
READ
COL b
READ
COL b
X = 1 cycle
n + 2
n + 1
D
D
OUT
OUT
X = 2 cycles
64Mb: x4, x8, x16 SDRAM
T5
T5
NOP
NOP
n + 2
n + 3
D
D
OUT
OUT
©2000 Micron Technology, Inc. All rights reserved.
T6
T6
NOP
NOP
n + 3
D
D
OUT
OUT
b
DON’T CARE
Commands
T7
NOP
D
OUT
b