MPC9448AC Integrated Device Technology (Idt), MPC9448AC Datasheet - Page 6

• Manufacturer Part Number: MPC9448AC
• Description: Clock Driver 2-IN LVCMOS 32-Pin TQFP Tray
• Manufacturer: Integrated Device Technology (Idt)

Specifications of MPC9448AC

• Package: 32TQFP
• Configuration: 1 x 2:1
• Input Signal Type: LVCMOS/LVPECL
• Maximum Output Frequency: 350 MHz
• Maximum Quiescent Current: 2 mA
• Operating Supply Voltage: 2.5|3.3 V

IDT™ / ICS™ LVCMOS 1:12 CLOCK FANOUT BUFFER
MPC9448
3.3V/2.5V LVCMOS 1:12 CLOCK FANOUT BUFFER
Driving Transmission Lines
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user, the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of 17 Ω (V
the outputs can drive either parallel or series terminated
transmission lines. For more information on transmission
lines, the reader is referred to Freescale application note
AN1091. In most high performance clock networks, point-to-
point distribution of signals is the method of choice. In a point-
to-point scheme, either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50 Ω resistance to V
thus, only a single terminated line can be driven by each
output of the MPC9448 clock driver. For the series terminated
case, however, there is no DC current draw; thus, the outputs
can drive multiple series terminated lines.
an output driving a single series terminated line versus two
series terminated lines in parallel. When taken to its extreme,
the fanout of the MPC9448 clock driver is effectively doubled
due to its capability to drive multiple lines at V
IN
IN
The MPC9448 clock driver was designed to drive high-
This technique draws a fairly high level of DC current ,and
CLK_STOP
Q0 to Q11
Figure 4. Single versus Dual Transmission Lines
CCLK or
PCLK
Figure 3. Output Clock Stop (CLK_STOP)
MPC9448
MPC9448
BufferR
Output
Output
Buffer
17Ω
17Ω
CC
Timing Diagram
÷2.
R
R
R
S
S
S
= 33Ω
= 33Ω
= 33Ω
Z
Z
Z
O
O
O
= 50Ω
= 50Ω
= 50Ω
Figure 4
CC
APPLICATION INFORMATION
CC
= 3.3 V.
= 3.3 V),
illustrates
OutA
OutB0
OutB1
6
results of an output driving a single line versus two lines. In
both cases, the drive capability of the MPC9448 output buffer
is more than sufficient to drive 50 Ω transmission lines on the
incident edge. Note from the delay measurements in the
simulations, a delta of only 43 ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output-to-output skew of the MPC9448. The output waveform
in
by the impedance mismatch seen looking into the driver. The
parallel combination of the 33 Ω series resistor plus the
output impedance does not match the parallel combination of
the line impedances. The voltage wave launched down the
two lines will equal:
unity reflection coefficient, to 2.5 V. It will then increment
towards the quiescent 3.0 V in steps separated by one round
trip delay (in this case 4.0 ns).
Figure 5
The waveform plots in
At the load end, the voltage will double, due to the near
3.0
2.5
2.0
1.5
1.0
0.5
0
shows a step in the waveform. This step is caused
Figure 5. Single versus Dual Line
t
2
D
V
Z
R
R
V
= 3.8956
OutA
0
In
L
L
S
0
Termination Waveforms
= V
= 50 Ω || 50 Ω
= 33 Ω || 33 Ω
= 17 Ω
= 3.0 (25 ÷ (16.5+17+25)
= 1.28 V
4
S
(Z
0
Figure 5
÷ (R
6
Time (ns)
t
D
S
+R
= 3.9386
OutB
MPC9448
show the simulation
8
0
+Z
0
))
10
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