MPC9448AC Integrated Device Technology (Idt), MPC9448AC Datasheet - Page 10

• Manufacturer Part Number: MPC9448AC
• Description: Clock Driver 2-IN LVCMOS 32-Pin TQFP Tray
• Manufacturer: Integrated Device Technology (Idt)

Specifications of MPC9448AC

• Package: 32TQFP
• Configuration: 1 x 2:1
• Input Signal Type: LVCMOS/LVPECL
• Maximum Output Frequency: 350 MHz
• Maximum Quiescent Current: 2 mA
• Operating Supply Voltage: 2.5|3.3 V

IDT™ / ICS™ LVCMOS 1:12 CLOCK FANOUT BUFFER
MPC9448
3.3V/2.5V LVCMOS 1:12 CLOCK FANOUT BUFFER
The pin-to-pin skew is defined as the worst case differ-
ence in propagation delay between any similar delay
path within a single device.
Figure 13. Propagation Delay (t
PCLK
PCLK
The time from the output controlled edge to the non-
controlled edge, divided by the time between output
controlled edges, expressed as a percentage.
Q
Figure 15. Output-to-Output Skew t
The variation in cycle time of a signal between ad-
jacent cycles, over a random sample of adjacent
cycle pairs.
X
Figure 17. Output Duty Cycle (DC)
Figure 19. Cycle-to-Cycle Jitter
T
N
t
P
V
t
PP
P(LH)
T
N+1
t
T
SK(LH)
DC = (t
0
P ?
t
P(HL)
T
0
PD
T
x 100%)
JIT(CC)
) Test Reference
t
SK(HL)
= |T
SK(LH, HL)
N
-T
V
V
GND
V
V
GND
N+1
CC
CC
CC
CC
V
V
GND
CC
CC
÷2
÷2
|
V
GND
÷2
CC
10
Figure 20. Setup and Hold Time (t
Figure 16. Output Pulse Skew (t
CLK_STOP
Figure 14. Propagation Delay (t
Figure 18. Output Transition Time Test Reference
CCLK
CCLK
Q
t
Q
CCLK
F
PCLK
X
X
t
P(LH)
t
P(LH)
t
SK(P)
t
S
= | t
PLH
t
P(HL)
t
t
H
R
t
– t
P(HL)
MPC9448
PHL
SK(P)
V
PD
S
|
CC
, t
) Test Reference
0.55
=3.3 V
2.4
H
) Test Reference
) Test Reference
REV 6 JULY 11, 2006
V
CC
1.8 V
0.6 V
=2.5 V
V
V
GND
V
V
GND
V
V
GND
V
V
GND
CC
CC
CC
CC
CC
CC
CC
CC
V
V
GND
V
V
GND
÷2
÷2
÷2
÷2
CC
CC
CC
CC
÷2
÷2