MPC9448AC Integrated Device Technology (Idt), MPC9448AC Datasheet

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MPC9448AC

Manufacturer Part Number
MPC9448AC
Description
Clock Driver 2-IN LVCMOS 32-Pin TQFP Tray
Manufacturer
Integrated Device Technology (Idt)
Datasheet

Specifications of MPC9448AC

Package
32TQFP
Configuration
1 x 2:1
Input Signal Type
LVCMOS/LVPECL
Maximum Output Frequency
350 MHz
Maximum Quiescent Current
2 mA
Operating Supply Voltage
2.5|3.3 V

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IDT™ / ICS™ LVCMOS 1:12 CLOCK FANOUT BUFFER
3.3 V/2.5 V LVCMOS 1:12 Clock
Fanout Buffer
1:12 clock fanout buffer targeted for high performance clock tree applications.
With output frequencies up to 350 MHz and output skews less than 150 ps, the
device meets the needs of most demanding clock applications.
Features
Functional Description
output provides a precise copy of the input signal with a near zero skew. The outputs buffers support driving of 50 Ω terminated
transmission lines on the incident edge. Each output is capable of driving either one parallel terminated or two series terminated
transmission lines.
tion systems. The MPC9448 CLK_STOP control is synchronous to the falling edge of the input clock. It allows the start and stop
of the output clock signal only in a logic low state, thus eliminating potential output runt pulses. Applying the OE control will force
the outputs into high-impedance mode.
a 2.5 V or 3.3 V power supply and an ambient temperature range of -40°C to +85°C. The MPC9448 is pin and function compatible
but performance-enhanced to the MPC948.
The Freescale Semiconductor, Inc. MPC9448 is a 3.3 V or 2.5 V compatible,
The MPC9448 is specifically designed to distribute LVCMOS compatible clock signals up to a frequency of 350 MHz. Each
Two selectable, independent clock inputs are available, providing support of LVCMOS and differential LVPECL clock distribu-
All inputs have an internal pull-up or pull-down resistor preventing unused and open inputs from floating. The device supports
32-lead Pb-free package available
applications
Pin and function compatible to MPC948
12 LVCMOS compatible clock outputs
Selectable LVCMOS and differential LVPECL compatible clock inputs
Maximum clock frequency of 350 MHz
Maximum clock skew of 150 ps
Synchronous output stop in logic low state eliminates output runt pulses
High-impedance output control
3.3 V or 2.5 V power supply
Drives up to 24 series terminated clock lines
Ambient temperature range -40°C to +85°C
32-Lead LQFP packaging
Supports clock distribution in networking, telecommunication and computing
1
CLOCK FANOUT BUFFER
3.3 V/2.5 V LVCMOS 1:12
32-LEAD LQFP PACKAGE
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
LOW VOLTAGE
CASE 873A-03
CASE 873A-03
MPC9448
FA SUFFIX
AC SUFFIX
REV 5 JULY 11, 2006
MPC9448

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MPC9448AC Summary of contents

Page 1

V/2.5 V LVCMOS 1:12 Clock Fanout Buffer The Freescale Semiconductor, Inc. MPC9448 2.5 V compatible, 1:12 clock fanout buffer targeted for high performance clock tree applications. With output frequencies up to 350 MHz and ...

Page 2

MPC9448 3.3V/2.5V LVCMOS 1:12 CLOCK FANOUT BUFFER V CC PCLK 0 PCLK CCLK CLK_SEL V CC CLK_STOP SYNC V CC (All input resistors have a value of 25 kΩ) OE Figure 1. Logic Diagram Table 1. Function ...

Page 3

MPC9448 3.3V/2.5V LVCMOS 1:12 CLOCK FANOUT BUFFER Table 3. Absolute Maximum Ratings Symbol Characteristics V Supply Voltage Input Voltage Output Voltage OUT I DC Input Current Output Current OUT T Storage ...

Page 4

MPC9448 3.3V/2.5V LVCMOS 1:12 CLOCK FANOUT BUFFER Table 6. AC Characteristics (V CC Symbol Characteristics f Input Frequency ref f Maximum Output Frequency MAX V Peak-to-Peak Input Voltage PP (2) V Common Mode Range CMR t Reference Input Pulse Width ...

Page 5

MPC9448 3.3V/2.5V LVCMOS 1:12 CLOCK FANOUT BUFFER Table 8. AC Characteristics (V CC Symbol Characteristics f Input Frequency ref f Maximum Output Frequency MAX V Peak-to-peak input voltage PP (2) V Common Mode Range CMR t Reference Input Pulse Width ...

Page 6

MPC9448 3.3V/2.5V LVCMOS 1:12 CLOCK FANOUT BUFFER CCLK or PCLK CLK_STOP Q0 to Q11 Figure 3. Output Clock Stop (CLK_STOP) Timing Diagram Driving Transmission Lines The MPC9448 clock driver was designed to drive high- speed signals in a terminated transmission ...

Page 7

MPC9448 3.3V/2.5V LVCMOS 1:12 CLOCK FANOUT BUFFER Since this step is well above the threshold region, it will not cause any false clock triggering; however, designers may be uncomfortable with unwanted reflections on the line. To better match the impedances ...

Page 8

MPC9448 3.3V/2.5V LVCMOS 1:12 CLOCK FANOUT BUFFER T should be selected according to the MTBF system J,MAX requirements, and Figure 9 R can be derived from thja Figure 10. The R represent data based on 1S2P boards. thja Using 2S2P ...

Page 9

MPC9448 3.3V/2.5V LVCMOS 1:12 CLOCK FANOUT BUFFER The Following Figures Illustrate the Measurement Reference for the MPC9448 Clock Driver Circuit Pulse Generator Ω Figure 11. CCLK MPC9448 AC Test Reference for V Differential Pulse Generator Z = ...

Page 10

MPC9448 3.3V/2.5V LVCMOS 1:12 CLOCK FANOUT BUFFER PCLK V PP PCLK P(LH) Figure 13. Propagation Delay (t t SK(LH) The pin-to-pin skew is defined as the worst case differ- ence in propagation delay between any similar ...

Page 11

MPC9448 3.3V/2.5V LVCMOS 1:12 CLOCK FANOUT BUFFER D1/2 PIN 1 INDEX E1 D/2 4X 0. 28X SEATING PLANE C DETAIL AD 8X (θ1˚ (S) A1 ...

Page 12

MPC9448 3.3V/2.5V LVCMOS 1:12 CLOCK FANOUT BUFFER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 netcom@idt.com 408-284-8200 480-763-2056 Fax: 408-284-2775 Corporate Headquarters Asia Pacific and Japan Integrated Device Technology, Inc. Integrated Device ...

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