PI7C21P100BEVB Pericom Semiconductor, PI7C21P100BEVB Datasheet - Page 5
PI7C21P100BEVB
Manufacturer Part Number
PI7C21P100BEVB
Description
MCU, MPU & DSP Development Tools 3 Port PCI Bridge Eval Brd
Manufacturer
Pericom Semiconductor
Specifications of PI7C21P100BEVB
Lead Free Status / RoHS Status
Not Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Not Compliant
TABLE OF CONTENTS
1
2
3
4
5
6
3.1
3.2
3.3
4.1
4.2
4.3
4.4
5.1
5.2
DESCRIPTION................................................................................................................................... 9
FEATURES ......................................................................................................................................... 9
SIGNAL DEFINITIONS.................................................................................................................. 10
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.2.7
3.2.8
3.2.9
PCI BUS OPERATION.................................................................................................................... 22
4.2.1
4.2.2
4.2.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.4.1
4.4.2
4.4.3
4.4.4
TRANSACTION ORDERING ........................................................................................................ 32
CLOCKS............................................................................................................................................ 34
4.2.1.1
4.2.1.2
4.2.1.3
4.2.1.4
4.3.1.1
4.3.1.2
4.3.1.3
4.3.1.4
4.3.3.1
4.3.3.2
4.3.5.1
4.3.5.2
4.3.5.3
SIGNAL TYPES ....................................................................................................................... 10
SIGNALS .................................................................................................................................. 10
PIN LIST ................................................................................................................................... 19
TYPES OF TRANSACTIONS ................................................................................................. 22
WRITE TRANSACTIONS ....................................................................................................... 23
READ TRANSACTIONS......................................................................................................... 25
CONFIGURATION TRANSACTIONS ................................................................................... 29
GENERAL ORDERING GUIDELINES .................................................................................. 33
ORDERING RULES................................................................................................................. 33
PRIMARY BUS INTERFACE SIGNALS............................................................................... 10
PRIMARY BUS INTERFACE SIGNALS – 64-BIT EXTENSION.......................................... 12
SECONDARY BUS INTERFACE SIGNALS......................................................................... 13
SECONDARY BUS INTERFACE SIGNALS – 64-BIT EXTENSION.................................... 14
CLOCK SIGNALS................................................................................................................. 15
STRAPPING PINS AND MISCELLANEOUS SIGNALS ...................................................... 16
JTAG BOUNDARY SCAN AND TEST SIGNALS ................................................................. 17
TEST SIGNALS..................................................................................................................... 18
POWER AND GROUND SIGNALS...................................................................................... 18
MEMORY WRITE TRANSACTIONS .................................................................................... 23
DELAYED/SPLIT WRITE TRANSACTIONS........................................................................ 25
IMMEDIATE WRITE TRANSACTIONS ............................................................................... 25
MEMORY READ TRANSACTIONS...................................................................................... 26
I/O READ.............................................................................................................................. 27
CONFIGURATION READ ................................................................................................... 27
NON-PREFETCHABLE AND DWORD READS.................................................................. 28
PREFETCHABLE READS.................................................................................................... 28
DYNAMIC PREFETCH (CONVENTIONAL PCI MODE ONLY) ........................................ 29
TYPE 0 ACCESS TO PI7C21P100....................................................................................... 30
TYPE 1 TO TYPE 0 CONVERSION ..................................................................................... 30
TYPE 1 TO TYPE 1 FORWARDING.................................................................................... 31
SPECIAL CYCLES ............................................................................................................... 32
PCI-X TO PCI-X ....................................................................................................................... 24
PCI TO PCI................................................................................................................................ 24
PCI TO PCI-X............................................................................................................................ 24
PCI-X TO PCI............................................................................................................................ 25
PCI-X TO PCI-X ....................................................................................................................... 26
PCI TO PCI................................................................................................................................ 26
PCI TO PCI-X............................................................................................................................ 26
PCI-X TO PCI............................................................................................................................ 27
TYPE 1 CONFIGURATION READ ......................................................................................... 27
TYPE 0 CONFIGURATION READ ......................................................................................... 27
PCI-X TO PCI-X AND PCI-X TO PCI .................................................................................... 28
PCI TO PCI................................................................................................................................ 28
PCI TO PCI-X............................................................................................................................ 29
Page 5 of 77
ADVANCE INFORMATION
July 5, 2005 Revision 1.07
2-PORT PCI-X BRIDGE
PI7C21P100