PI7C21P100BEVB Pericom Semiconductor, PI7C21P100BEVB Datasheet - Page 31

• Manufacturer Part Number: PI7C21P100BEVB
• Description: MCU, MPU & DSP Development Tools 3 Port PCI Bridge Eval Brd
• Manufacturer: Pericom Semiconductor

Specifications of PI7C21P100BEVB

• Lead Free Status / RoHS Status: Not Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Not Compliant

4.4.3
Table 4-4 DEVICE NUMBER TO IDSEL
When PI7C21P100 translates the Type 1 transaction to a Type 0 transaction on the secondary
interface, it performs the following translations to the address:
PI7C21P100 asserts a unique address line based on the device number. These address lines
may be used as secondary bus IDSEL signals. The mapping of the address lines depends on
the device number in the address bits P_AD[15:11] for Type 1 transactions. Table 4-4
presents the mapping that PI7C21P100 uses.
PI7C21P100 forwards Type 1 to Type 0 configuration read or write transactions as delayed
transactions in PCI mode or as split transactions in PCI-X mode.
TYPE 1 TO TYPE 1 FORWARDING
Type 1 to Type 1 transaction forwarding provides a hierarchical configuration mechanism
when two or more levels of PCI-to-PCI bridges are used.
When PI7C21P100 detects a Type 1 configuration transaction intended for a PCI/PCI-X bus
downstream from the secondary interface, PI7C21P100 forwards the transaction unchanged to
the secondary interface. Ultimately, this transaction is translated to a Type 0 configuration
command or to a special cycle transaction by a downstream PCI bridge. Downstream Type 1
to Type 1 forwarding occurs when the following conditions are met during the address phase:
The bus number in address field P_AD[23:16] is equal to the value in the secondary bus
number register in configuration space.
P_CBE[3:0]# is a configuration read or configuration write transaction.
Sets the lowest two address bits on S_AD[1:0] to 00.
Decodes the device number and drives the bit pattern specified in Table 4-4 on
S_AD[31:16] for the purpose of asserting the device’s IDSEL signal.
Sets S_AD[15:11] to 0 if the secondary bus is operating in conventional PCI mode
(device number is passed through unchanged in PCI-X mode)
Leaves unchanged the function number and register number fields.
Device Number
10h – 1Eh
1Fh
Ah
Bh
Ch
Dh
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Eh
Fh
10000 – 11110
P_AD[15:11]
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00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
11111
or, may convert to a special cycle transaction described
Secondary IDSEL S_AD[31:16]
ADVANCE INFORMATION
0000 0000 0000 0001
0000 0000 0000 0010
0000 0000 0000 0100
0000 0000 0000 1000
0000 0000 0001 0000
0000 0000 0010 0000
0000 0000 0100 0000
0000 0000 1000 0000
0000 0001 0000 0000
0000 0010 0000 0000
0000 0100 0000 0000
0000 1000 0000 0000
0001 0000 0000 0000
0010 0000 0000 0000
0100 0000 0000 0000
1000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
in section 4.4.4
July 5, 2005 Revision 1.07
2-PORT PCI-X BRIDGE
PI7C21P100