PI7C21P100BEVB Pericom Semiconductor, PI7C21P100BEVB Datasheet - Page 27

• Manufacturer Part Number: PI7C21P100BEVB
• Description: MCU, MPU & DSP Development Tools 3 Port PCI Bridge Eval Brd
• Manufacturer: Pericom Semiconductor

Specifications of PI7C21P100BEVB

• Lead Free Status / RoHS Status: Not Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Not Compliant

4.3.1.4
4.3.2
4.3.3
4.3.3.1
4.3.3.2
PI7C21P100 must translate the conventional PCI memory read multiple command to the
memory read block PCI-X command. Bits [21:20] offset 40h and bits [5:4] offset 40h control
the mode of prefetching for memory read multiple transactions in the prefetchable range on
the secondary and primary bus respectively. The default is a full prefetch, limited to the value
set by bits [14:12] offset 40h. The default value is 512 bytes, or an entire read buffer. Using
a value greater than this is possible, but it may be constrained by the setting of the split
transaction commitment limit value in the upstream or downstream split transaction register,
since the target bus is in PCI-X mode. Data fetching operations will be disconnected at all
1MB boundaries.
PI7C21P100 translates PCI-X memory read DWORD commands into conventional PCI
memory read commands. PI7C21P100 translates a PCI-X memory read block command into
one of three conventional PCI memory read commands based on the byte count and starting
address. If the starting address and byte count are such that only a single DWORD (or less) is
being read, the conventional PCI transaction uses the memory read command. If the PCI-X
transaction reads more than one DWORD, but does not cross a cache line boundary (indicated
by the Cache Line Size register in the conventional Configuration Space header), the
conventional transaction uses the memory read line command. If the PCI-X transaction
crosses a cache line boundary, the conventional transaction uses the memory read multiple
command. If a disconnect occurs before the byte count of the PCI-X memory read block
command is exhausted, the PI7C21P100 continues to issue the command until all the bytes in
the count are received. PI7C21P100 disconnects once the buffer is filled and prefetches more
data as 128-byte sectors of the buffer become free when split completion data is returned to
the originator, until the byte count is exhausted.
I/O READ
The I/O Read command is not translated and fetches a DWORD of data. The command will
either be split in the PCI-X mode or delayed in the conventional PCI mode.
CONFIGURATION READ
The Type 1 configuration read command is only accepted on the primary interface. The
command will either be split in the PCI-X mode or delayed in the conventional PCI mode.
The Type 0 configuration read command is accepted on either the primary or secondary
interface. The command returns immediate data on the primary interface regardless of the
interface mode. On the secondary interface the command is treated either as a split transaction
in PCI-X mode or as a delayed transaction in the PCI mode.
PCI-X TO PCI
TYPE 1 CONFIGURATION READ
TYPE 0 CONFIGURATION READ
Page 27 of 77
ADVANCE INFORMATION
July 5, 2005 Revision 1.07
2-PORT PCI-X BRIDGE
PI7C21P100