74HCT7046AD-T NXP Semiconductors, 74HCT7046AD-T Datasheet - Page 35

Phase Locked Loops (PLL) PHASED-LOCKED LOOP W/LOCK DTCT

74HCT7046AD-T

Manufacturer Part Number
74HCT7046AD-T
Description
Phase Locked Loops (PLL) PHASED-LOCKED LOOP W/LOCK DTCT
Manufacturer
NXP Semiconductors
Type
PLLr
Datasheet

Specifications of 74HCT7046AD-T

Number Of Circuits
1
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
5 V
Package / Case
SO-16
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74HCT7046AD,118
Philips Semiconductors
The maximum permitted phase error
must be defined, before t
defined using the following formula:
Using this calculated value in Fig.32,
it is possible to define the value of
C
36 and f
and using Fig.32, it can be seen that
C
With the addition of one retriggerable
monostable (e.g. “123”, “423” or
“4538”) a steady state LOW and
HIGH indication can be obtained, as
shown in Fig.33.
December 1990
t
LD
t
LD
LD
LD
Phase-locked-loop with lock detector
, e.g. assuming the phase error is
is 26 pF.
=
=
--------- -
360
36
----------- -
360
IN
max
= 2 MHz:
-----------------
2 MHz
----- -.
f
1
IN
1
=
50 ns,
LD
can be
Fig.33 Steady state signal for lock indication.
35
74HC/HCT7046A
Product specification

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