TDA8263HN/C1-T NXP Semiconductors, TDA8263HN/C1-T Datasheet - Page 14

• Manufacturer Part Number: TDA8263HN/C1-T
• Description: Tuners INTEGRATED SATELLITE TUNER
• Manufacturer: NXP Semiconductors

Specifications of TDA8263HN/C1-T

• Bus Type: I2C
• Maximum Agc: 60 dB
• Maximum Frequency: 2175 MHz
• Minimum Frequency: 950 MHz
• Modulation Technique: QPSK
• Mounting Style: SMD/SMT
• Package / Case: HVQFN-32
• Function: Satellite
• Noise Figure: 7.7 dB
• Operating Supply Voltage: 3.3 V
• Supply Voltage (min): 3.15 V
• Supply Voltage (max): 3.45 V
• Minimum Operating Temperature: - 20 C
• Maximum Operating Temperature: + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: TDA8263HN/C1,518

Philips Semiconductors
Table 28:
[1]
9397 750 13193
Product data sheet
Byte
0
1
X can be 1 or 0 and needs to be masked in the microcontrollers’ software; MSB is transmitted first.
MSB
7
POR
1
I
2
C-bus read mode map
11.10 Bit description I
11.8 Data transfer in read mode
11.9 I
6
LOCK
INLEVEL1
Table 25:
These bits control the voltage threshold for the ACDN comparator. The ACUP and ACDN
comparators sense the LC VCO tuning voltage at pin VT.
[1]
[2]
Table 26:
This register modifies the baseband bias current through different parts: Output buffer or other
amplifier.
The data transfer in read mode use the following pattern.
Table 27:
Table 29:
BBIAS[3:0]
Binary value
START address
2
SELVTL1
C-bus table in read mode
Typical values at nominal process and room temperature.
The recommended value is SELVTL[1:0] = 01 (decimal 1).
POR
0
0
1
1
0
1
Minimum voltage tuning threshold for calibration control; bits SELVTL[1:0]
Baseband bias current control; bits BBIAS[3:0]
I
Power-on reset; bit POR
[1]
2
C-bus read mode data transfer pattern
5
ACUP
INLEVEL0
Action
Normal operation
This bit is set to logic 1 at the V
after the first read of the IC.
When V
in internal I
SELVTL0
0
1
0
1
Value
The allowed value is BBIAS[3:0] = 1101 (decimal 13). The product is
specified only with this value, other settings may lead to different
performance.
2
Rev. 01 — 14 December 2004
CC(DIG)
C-bus read mode
2
C-bus registers programming.
Decimal
0
1
2
3
4
ACDN
DW4
ack
falls below 2 V typical, this bit is set to logic 1. This is to prevent loss
data 1
Threshold VTL (V)
0.6
0.5
0.4
0.3
3
ERRORCAL X
DW3
CC(DIG)
power supply ramp-up. It is reset to logic 0
ack
2
DW2
[1] [2]
Fully integrated satellite tuner
data 2
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
TDA8263HN
1
X
DW1
ack
LSB
0
X
DW0
STOP
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