ATA5812-PLQW80 Atmel, ATA5812-PLQW80 Datasheet - Page 35
![RF Transceiver RF Data Control Transceiver](/photos/30/99/309912/qfn-48_sml.jpg)
ATA5812-PLQW80
Manufacturer Part Number
ATA5812-PLQW80
Description
RF Transceiver RF Data Control Transceiver
Manufacturer
Atmel
Datasheet
1.ATA5811-PLHC.pdf
(92 pages)
Specifications of ATA5812-PLQW80
Wireless Frequency
226 KHz
Interface Type
4-Wire SPI
Noise Figure
7 dB
Output Power
10 dBm
Operating Supply Voltage
2.4 V to 5.25 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Package / Case
QFN-48
Maximum Data Rate
20 Kbps
Minimum Operating Temperature
- 40 C
Modulation
ASK, FSK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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9.2
9.3
9.3.1
4689F–RKE–08/06
TX/RX Data Buffer
Control Register
Control Register 1 (ADR 0)
The TX/RX data buffer is used to handle the data transfer during RX and TX operations.
To use the transceiver in different applications it can be configured by a connected microcontrol-
ler via the 4-wire serial interface.
Table 9-1.
Table 9-2.
Table 9-3.
Table 9-4.
Table 9-5.
IR1
IR1
OPM1
0
0
1
1
0
0
1
1
AVCC_EN
0
0
1
1
FS
0
1
0
1
IR0
IR0
0
1
0
1
0
1
0
1
OPM0
Function (RX Mode)
Pin IRQ is set to 1 if 4 received bytes are in the TX/RX data buffer or a receiving error
occurred
Pin IRQ is set to 1 if 8 received bytes are in the TX/RX data buffer or a receiving error
occurred
Pin IRQ is set to 1 if 12 received bytes are in the TX/RX data buffer or a receiving error
occurred (default)
Pin IRQ is set to 1 if a receiving error occurred
Function (TX Mode)
Pin IRQ is set to 1 if 4 bytes still are in the TX/RX data buffer or the TX data buffer is empty
Pin IRQ is set to 1 if 8 bytes still are in the TX/RX data buffer or the TX data buffer is empty
Pin IRQ is set to 1 if 12 bytes still are in the TX/RX data buffer or the TX data buffer is empty
(default)
Pin IRQ is set to 1 if the TX data buffer is empty
Control Register 1 (Function of Bit 7 and Bit 6 in RX Mode)
Control Register 1 (Function of Bit 7 and Bit 6 in TX Mode)
Control Register 1 (Function of Bit 5)
Control Register 1 (Function of Bit 4)
Control Register 1 (Function of Bit 2 and Bit 1)
0
1
0
1
(default)
Enables AVCC, if the ATA5811/
Function
433/868 MHz
315 MHz
Function
Function
Idle mode (default)
TX mode
RX polling mode
RX mode
ATA5812
is in AUX mode
ATA5811/ATA5812
35
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