MAX11008BETM+ Maxim Integrated Products, MAX11008BETM+ Datasheet - Page 54

• Manufacturer Part Number: MAX11008BETM+
• Description: RF Wireless Misc IC CTLR LDMOS BIAS DUAL
• Manufacturer: Maxim Integrated Products

Specifications of MAX11008BETM+

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Dual RF LDMOS Bias Controller with
Nonvolatile Memory
The A_HIST register bits A_HIST[3:0] set the APC hys-
teresis limits for both channel 1 and channel 2 V
calculations. After a new APC sample, the device pro-
ceeds in performing a V
differs from the previous sample used for a V
culation by an amount greater than the hysteresis set-
ting (see Table 16e). Set APCCOMP_ and TCOMP_ to 0
before A_HIST is changed.
DAC_[11:0] set the value of the DAC Input registers
(see Table 17). Bits D[15:12] are don’t-care bits. The
GATE_ output is not updated with this value until it is
transferred to the DAC Output register. Write to the
Load DAC register to transfer the contents of the DAC
Input register to the DAC Output register. Write directly
to the DAC Input register to manipulate the DAC output
without triggering a V
DAC_[11:0] set the values of the input and output regis-
ters of the respective DACs (see Table 18). Writing to
Table 13a. Channel 2 Averaging Equation
(T2AVGCTL)
Table 13b. Channel 2 Difference Limiter Bits (T2LIMIT[2:0])
Table 13c. APC Parameter Source Select Bits (APCSRC_1, APCSRC_0)
54
DAC Input and Output Registers (IODAC1, IODAC2)
D15
APCSRC_1
DAC Input Registers (IDAC1, IDAC2) (Write Only)
0
1
______________________________________________________________________________________
D14
0
0
0
0
1
1
1
1
0
0
1
1
Average = average + 1/16 difference.
Average = average + 1/4 difference.
CHANNEL 2 AVERAGING EQUATION
APCSRC_0
GATE_
D13
0
0
1
1
0
0
1
1
0
1
0
1
GATE_
calculation.
calculation if that sample
Value stored in APC parameter register.
Reserved. Do not use.
Drain current samples.
External input samples (AIN input).
D12
0
1
0
1
0
1
0
1
(Write Only)
GATE_
GATE_
No limiting is applied.
Difference is limited to 1 LSB (1/8 of a degree).
Difference is limited to 3 LSBs (3/8 of a degree).
Difference is limited to 7 LSBs (7/8 of a degree).
Difference is limited to 15 LSBs (1 7/8 degrees).
Difference is limited to 31 LSBs (3 7/8 degrees).
Difference is limited to 63 LSBs (7 7/8 degrees).
Difference is limited to 127 LSBs (15 7/8 degrees).
cal-
APC PARAMETER SOURCE SELECT
this register does not trigger a V
the GATE_ output is immediately updated with the
value that is written to this register. Bits D[15:12] are
don’t-care bits. The contents of the DAC Input and
Output registers are not stored in the EEPROM.
The PGA Calibration Control register selects the PGA
calibration mode and controls when calibrations occur
(see Table 19). Bits D[15:3] are don’t-care bits. The
data contained in the PGA Calibration Control register
is stored in the EEPROM.
Set TRACK to 0 to perform the next PGA calibration in
acquisition mode, and set TRACK to 1 to perform the
next PGA calibration in tracking mode. Leave TRACK
set to 0 the first time a PGA calibration is performed
after power-up.
Set DOCAL to 1 to perform calibrations of PGA1 and
PGA2. DOCAL resets to 0 after the PGA calibration rou-
tine is complete. If either channel is powered down, the
PGA calibration for that channel is bypassed.
CHANNEL 2 DIFFERENCE LIMITER
PGA Calibration Control Register (PGACAL)
GATE_
calculation, but
(Write Only)