MAX11008BETM+ Maxim Integrated Products, MAX11008BETM+ Datasheet - Page 21

• Manufacturer Part Number: MAX11008BETM+
• Description: RF Wireless Misc IC CTLR LDMOS BIAS DUAL
• Manufacturer: Maxim Integrated Products

Specifications of MAX11008BETM+

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

A bus master initiates communication with a slave
device by issuing a START condition followed by the 7-
bit slave address and a read/write (R/W) bit (see Figure
7). When the device recognizes its slave address, it is
ready to accept or send data depending on the R/W
bit. When the MAX11008 recognizes its slave address,
it issues an ACK by pulling SDA low for one clock cycle
and is ready to accept or send data depending on the
R/W bit that was sent.
The MAX11008 has eight user-selectable slave address-
es, which are set through inputs A0, A1, and A2 (see
Table 1). This feature allows up to eight MAX11008
devices to share the same bus inputs. The 4 MSBs D[7:4]
are factory set, and the 3 LSBs are user-selectable.
Table 1. Slave Address Select
Figure 7. Slave Address Bits
Figure 8. F/S-Mode to HS-Mode Transfer
A2
0
0
0
0
1
1
1
1
SDA
SCL
SDA
A1
0
0
1
1
0
0
1
1
S
______________________________________________________________________________________
A0
0
1
0
1
0
1
0
1
0
1
0
1
Dual RF LDMOS Bias Controller with
0
2
1
2
ADDRESS
0101000
0101001
0101010
0101011
0101100
0101101
0101110
0101111
0
3
Slave Address
3
0
0
4
F/S MODE
1
4
1
5
At power-up, the bus timing is set for I
(F/S mode), which allows I
The MAX11008 can also operate in high-speed mode
(HS mode) to achieve I
See Figure 4 for I
Select HS mode by addressing all devices on the bus
with the HS-mode master code 0000 1XXX (X = don’t
care). After successfully receiving the HS-mode master
code, the MAX11008 issues a NACK, allowing SDA to
be pulled high for one clock cycle (see Figure 8). After
the NACK, the MAX11008 operates in HS mode. The
master must then send a repeated START (Sr) followed
by a slave address to initiate HS-mode communication.
If the master generates a STOP condition, the
A2
5
X
6
Nonvolatile Memory
A1
6
X
7
2
C bus timing.
A0
7
X
8
2
C clock rates up to 3.4MHz.
2
C clock rates up to 400kHz.
R/W
8
A
9
9
A
HS MODE
2
HS I
C fast-mode
Sr
Bus Timing
2
C Mode
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