MAX11008BETM+ Maxim Integrated Products, MAX11008BETM+ Datasheet - Page 22

• Manufacturer Part Number: MAX11008BETM+
• Description: RF Wireless Misc IC CTLR LDMOS BIAS DUAL
• Manufacturer: Maxim Integrated Products

Specifications of MAX11008BETM+

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Dual RF LDMOS Bias Controller with
Nonvolatile Memory
MAX11008 returns to F/S mode. Use a repeated START
condition in place of a STOP condition to leave the bus
active and the mode unchanged. Figure 9 summarizes
the data bit transfer format for HS-mode communication.
A write cycle begins with the bus master issuing a
START condition followed by 7 address bits (see Figure
5 and Table 1) and a write bit (R/W = 0). Once the
slave address is recognized and the write bit is
received, the MAX11008 (I
pulling SDA low for one clock cycle. The master then
sends the register address byte (command byte) to the
Figure 9. Data-Transfer Format in HS Mode
Figure 10. Write Cycle
22
S
______________________________________________________________________________________
4-BYTE WRITE CYCLE
1
S
MASTER TO SLAVE
SLAVE TO MASTER
Register Address/Data Bytes (Write Cycle)
MASTER TO SLAVE
SLAVE TO MASTER
ADDRESS
SLAVE
MASTER CODE
7
F/S MODE
1 1
W
A
REGISTER ADDRESS
2
C slave) issues an ACK by
N
BYTE
8
WHETHER TO READ OR WRITE TO
Sr
MSB DETERMINES
REGISTERS
1
A
SLAVE ADDRESS
DATA BYTE
8
R/W
1
A
slave. The MSB of the register address byte is the
read/write bit for the destination register address of the
slave and must be set to 0 for a write cycle (see the
Register Address Map section). After receiving the
byte, the slave issues another acknowledge, pulling
SDA low for one clock cycle. The master then writes
two data bytes, receiving an ACK from the slave after
each byte is sent. The master ends the write cycle by
issuing a STOP condition. When operating in HS mode,
a STOP condition returns the bus into F/S mode (see
the HS I
write cycle.
HS MODE
A
DATA BYTE
8
2
C Mode section). Figure 10 shows a complete
1
A
N BYTES + ACK
DATA
P OR Sr
1
NUMBER OF BITS
A
P
Sr
HS MODE CONTINUES
SLAVE ADD
F/S MODE