XC5VLX50-1FF676I Xilinx Inc, XC5VLX50-1FF676I Datasheet - Page 322
![FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 676-Pin FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX50-1FF676I
Manufacturer Part Number
XC5VLX50-1FF676I
Description
FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 676-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX50-1FF676I
Package
676FCBGA
Family Name
Virtex®-5
Device Logic Units
46080
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
440
Ram Bits
1769472
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
1769472
Number Of I /o
440
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
676-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF676-500-G - BOARD DEV VIRTEX 5 FF676HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 7: SelectIO Logic Resources
322
IDDR VHDL and Verilog Templates
ILOGIC Timing Models
ILOGIC Timing Characteristics
Table 7-4: IDDR Attributes
The Libraries Guide includes templates for instantiation of the IDDR primitive in VHDL
and Verilog.
This section describes the timing associated with the various resources within the ILOGIC
block.
Figure 7-6
T
X-Ref Target - Figure 7-6
Clock Event 1
•
•
DDR_CLK_EDGE
INIT_Q1
INIT_Q2
SRTYPE
CLK
CE1
IDOCKD
SR
Q1
Attribute Name
D
At time T
High at the CE1 input of the input register, enabling the input register for incoming
data.
At time T
input of the input register and is reflected on the Q1 output of the input register at
time T
.
illustrates ILOGIC register timing. When IDELAY is used, T
ICKQ
ICE1CK
IDOCK
Figure 7-6: ILOGIC Input Register Timing Characteristics
after Clock Event 1.
1
before Clock Event 1, the input signal becomes valid-High at the D
before Clock Event 1, the input clock enable signal becomes valid-
Sets the IDDR mode of operation with
respect to clock edge
Sets the initial value for Q1 port
Sets the initial value for Q2 port
Set/Reset type with respect to clock (C) ASYNC (default), SYNC
T
T
IDOCK
ICE1CK
www.xilinx.com
T
ICKQ
Description
2
3
OPPOSITE_EDGE (default),
SAME_EDGE,
SAME_EDGE_PIPELINED
0 (default), 1
0 (default), 1
4
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Possible Values
T
ISRCK
IDOCK
T
ICKQ
is replaced by
ug190_7_06_041206
5
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