XC5VLX50-1FF676I Xilinx Inc, XC5VLX50-1FF676I Datasheet - Page 288
![FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 676-Pin FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX50-1FF676I
Manufacturer Part Number
XC5VLX50-1FF676I
Description
FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 676-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX50-1FF676I
Package
676FCBGA
Family Name
Virtex®-5
Device Logic Units
46080
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
440
Ram Bits
1769472
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
1769472
Number Of I /o
440
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
676-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF676-500-G - BOARD DEV VIRTEX 5 FF676HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- XC5VLX30-1FFG324C PDF datasheet
- XC5VLX30-1FFG324C PDF datasheet #2
- XC5VLX30-1FFG324C PDF datasheet #3
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- Download datasheet (14Mb)
Chapter 6: SelectIO Resources
X-Ref Target - Figure 6-80
288
External Termination
DCI
SSTL18_II_DCI
SSTL18 Class II (1.8V)
R 0 = 20
SSTL18_II
Ω
2R
2R
Figure 6-80: SSTL18 (1.8V) Class II Unidirectional Termination
IOB
VRN
VRP
Figure 6-80
for SSTL Class II (1.8V).
Figure 6-81
for SSTL (1.8V) Class II.
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
R S = 20Ω
V
CCO
shows a sample circuit illustrating a valid unidirectional termination technique
shows a sample circuit illustrating a valid bidirectional termination technique
V
TT
= 1.8V
= 0.9V
IOB
R P = Z 0 = 50Ω
www.xilinx.com
Z 0
Z 0
R P = Z 0 = 50Ω
V
TT
IOB
V
= 0.9V
CCO
2R
2R
= 1.8V
VRP
VRN
IOB
V
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
REF
V
REF
= 0.9V
= 0.9V
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
SSTL18_II_DCI
SSTL18_II
+
–
ug190_6_75_030506
+
–
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