XC5VLX50-1FF676I Xilinx Inc, XC5VLX50-1FF676I Datasheet - Page 14
![FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 676-Pin FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX50-1FF676I
Manufacturer Part Number
XC5VLX50-1FF676I
Description
FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 676-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX50-1FF676I
Package
676FCBGA
Family Name
Virtex®-5
Device Logic Units
46080
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
440
Ram Bits
1769472
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
1769472
Number Of I /o
440
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
676-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF676-500-G - BOARD DEV VIRTEX 5 FF676HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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14
Chapter 5: Configurable Logic Blocks (CLBs)
FIFO Timing Models and Parameters
FIFO Applications
Built-in Error Correction
Legal Block RAM and FIFO Combinations
CLB Overview
CLB / Slice Timing Models
FIFO Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Cascading FIFOs to Increase Depth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Connecting FIFOs in Parallel to Increase Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
ECC Modes Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Top-Level View of the Block RAM ECC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 160
Block RAM and FIFO ECC Primitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Block RAM and FIFO ECC Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Block RAM and FIFO ECC Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
ECC Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
ECC Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Block RAM ECC Mode Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Creating a Deliberate Error in a 72-bit Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Creating Eight Parity Bits for a 64-bit Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Inserting a Single or Double Bit Error into a 72-bit Word . . . . . . . . . . . . . . . . . . . . . . 170
Block RAM ECC VHDL and Verilog Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Slice Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
General Slice Timing Model and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Slice Distributed RAM Timing Model and Parameters (Available in SLICEM only)204
Case 1: Writing to an Empty FIFO
Case 2: Writing to a Full or Almost Full FIFO
Case 3: Reading From a Full FIFO
Case 4: Reading From An Empty or Almost Empty FIFO
Case 5: Resetting All Flags
Case 6: Simultaneous Read and Write for Multirate FIFO
Standard ECC
ECC Encode-Only
ECC Decode-Only
Standard ECC Write Timing
Standard ECC Read Timing
Encode-Only ECC Write Timing
Encode-Only ECC Read Timing
Decode-Only ECC Write Timing
Decode-Only ECC Read Timing
CLB/Slice Configurations
Look-Up Table (LUT)
Storage Elements
Distributed RAM and Memory (Available in SLICEM only)
Read Only Memory (ROM)
Shift Registers (Available in SLICEM only)
Multiplexers
Designing Large Multiplexers
Fast Lookahead Carry Logic
Timing Parameters
Timing Characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
www.xilinx.com
(Figure
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
(Figure
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
(Figure
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
4-32)
4-31)
4-31)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
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. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
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. . . . . . . . . . . . . . . . . . . . . . 157
. . . . . . . . . . . . . . . . . . . . 180
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
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