XC3S1600E-5FGG400C Xilinx Inc, XC3S1600E-5FGG400C Datasheet - Page 218
![FPGA Spartan®-3E Family 1.6M Gates 33192 Cells 657MHz 90nm (CMOS) Technology 1.2V 400-Pin FBGA](/photos/6/72/67298/pk083-400_sml.jpg)
XC3S1600E-5FGG400C
Manufacturer Part Number
XC3S1600E-5FGG400C
Description
FPGA Spartan®-3E Family 1.6M Gates 33192 Cells 657MHz 90nm (CMOS) Technology 1.2V 400-Pin FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S1600E-5FGG400C
Package
400FBGA
Family Name
Spartan®-3E
Device Logic Cells
33192
Device Logic Units
3688
Device System Gates
1600000
Number Of Registers
29504
Maximum Internal Frequency
657 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
304
Ram Bits
663552
Number Of Logic Elements/cells
33192
Number Of Labs/clbs
3688
Total Ram Bits
663552
Number Of I /o
304
Number Of Gates
1600000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
400-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-XA3S1600E-UNI-G - KIT DEVELOPMENT AUTOMOTIVE ECU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S1600E-5FGG400C
Manufacturer:
XILINX
Quantity:
259
Company:
Part Number:
XC3S1600E-5FGG400C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC3S1600E-5FGG400C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
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Pinout Descriptions
Table 152: FG400 Package Pinout (Continued)
218
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO_L29N_1/LDC0
IO_L29P_1/HDC
IO_L30N_1/LDC2
IO_L30P_1/LDC1
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP/VREF_1
IP/VREF_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
IO
IO
IO
IO
IO
IO
IO
IO
IO/D5
IO/M1
IO/VREF_2
IO/VREF_2
IO_L01N_2/INIT_B
IO_L01P_2/CSO_B
IO_L03N_2/MOSI/CSI_B
IO_L03P_2/DOUT/BUSY
XC3S1200E
XC3S1600E
Pin Name
FG400
M20
W15
Ball
D18
C19
C20
G15
G18
H14
N14
N20
R16
R19
D19
G17
N17
R13
N11
E18
B20
L18
P15
E19
K18
K15
K19
T19
P13
Y13
T11
Y17
J15
R9
U4
U5
P8
Y5
Y7
Y3
V4
V5
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
DUAL
DUAL
DUAL
DUAL
VREF
VREF
DUAL
DUAL
VREF
VREF
DUAL
DUAL
DUAL
DUAL
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
www.xilinx.com
Table 152: FG400 Package Pinout (Continued)
Bank
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO_L04N_2
IO_L04P_2
IO_L06N_2
IO_L06P_2
IO_L07N_2
IO_L07P_2
IO_L09N_2/VREF_2
IO_L09P_2
IO_L10N_2
IO_L10P_2
IO_L12N_2
IO_L12P_2
IO_L13N_2
IO_L13P_2
IO_L15N_2/D6/GCLK13
IO_L15P_2/D7/GCLK12
IO_L16N_2/D3/GCLK15
IO_L16P_2/D4/GCLK14
IO_L18N_2/D1/GCLK3
IO_L18P_2/D2/GCLK2
IO_L19N_2/DIN/D0
IO_L19P_2/M0
IO_L21N_2
IO_L21P_2
IO_L22N_2/VREF_2
IO_L22P_2
IO_L24N_2
IO_L24P_2
IO_L25N_2
IO_L25P_2
IO_L27N_2/A22
IO_L27P_2/A23
IO_L28N_2
IO_L28P_2
IO_L30N_2/A20
IO_L30P_2/A21
XC3S1200E
XC3S1600E
Pin Name
DS312-4 (v3.8) August 26, 2009
Product Specification
FG400
W10
W12
W13
Ball
R10
U16
P10
V11
V10
Y12
Y11
U12
V12
U13
V13
P14
R14
Y14
Y15
T15
U15
V16
W4
W8
W9
U7
R7
U9
Y4
T6
T5
V7
T7
V8
V9
Y8
Y9
DUAL/
DUAL/
DUAL/
DUAL/
DUAL/
DUAL/
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
VREF
DUAL
DUAL
VREF
DUAL
DUAL
DUAL
DUAL
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
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