XC3S1600E-4FGG484I Xilinx Inc, XC3S1600E-4FGG484I Datasheet - Page 172
![FPGA Spartan®-3E Family 1.6M Gates 33192 Cells 572MHz 90nm (CMOS) Technology 1.2V 484-Pin FBGA](/photos/6/72/67299/pk081-484_sml.jpg)
XC3S1600E-4FGG484I
Manufacturer Part Number
XC3S1600E-4FGG484I
Description
FPGA Spartan®-3E Family 1.6M Gates 33192 Cells 572MHz 90nm (CMOS) Technology 1.2V 484-Pin FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S1600E-4FGG484I
Package
484FBGA
Family Name
Spartan®-3E
Device Logic Cells
33192
Device Logic Units
3688
Device System Gates
1600000
Number Of Registers
29504
Maximum Internal Frequency
572 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
376
Ram Bits
663552
Number Of Logic Elements/cells
33192
Number Of Labs/clbs
3688
Total Ram Bits
663552
Number Of I /o
376
Number Of Gates
1600000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-BBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-XA3S1600E-UNI-G - KIT DEVELOPMENT AUTOMOTIVE ECU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S1600E-4FGG484I
Manufacturer:
XILINX
Quantity:
140
Company:
Part Number:
XC3S1600E-4FGG484I
Manufacturer:
XILINX
Quantity:
250
Company:
Part Number:
XC3S1600E-4FGG484I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC3S1600E-4FGG484I
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Pinout Descriptions
VQ100 Footprint
In
orientation.
172
16
Figure
1
2
0
I/O: Unrestricted,
general-purpose user I/O
INPUT: Unrestricted,
general-purpose input pin
CONFIG: Dedicated
configuration pins
N.C.: Not connected
81, note pin 1 indicator in top-left corner and logo
IO_L02N_3/VREF_3
IO_L03P_3/LHCLK0
IO_L03N_3/LHCLK1
IO_L04P_3/LHCLK2
IO_L04N_3/LHCLK3
IO_L05P_3/LHCLK4
IO_L05N_3/LHCLK5
IO_L06P_3/LHCLK6
IO_L06N_3/LHCLK7
IO_L01P_2/CSO_B 24
IO_L01N_2/INIT_B 25
IO_L01N_3
IO_L07N_3 23
IO_L01P_3
IO_L02P_3
IO_L07P_3 22
PROG_B
VCCAUX
VCCO_3
VCCO_3 20
VCCINT
GND
GND
GND
IP 13
10
11
12
14
15
16
17
18
19
21
1
2
3
4
5
6
7
8
9
Figure 81: VQ100 Package Footprint (top view)
21
24
12
4
DUAL: Configuration pin, then
possible user-I/O
CLK: User I/O, input, or global
buffer input
JTAG: Dedicated JTAG port
pins
GND: Ground
www.xilinx.com
Bank 0
Bank 2
4
8
4
4
VREF: User I/O or input
voltage reference for bank
VCCO: Output voltage supply
for bank
VCCINT: Internal core supply
voltage (+1.2V)
VCCAUX: Auxiliary supply
voltage (+2.5V)
75
74 VCCAUX
73 VCCO_1
72
71 IO_L07N_1
70 IO_L07P_1
69 IP/VREF_1
68
67
66
65
64
63
62
61
60
59
58 IO_L02N_1
57 IO_L02P_1
56
55 VCCO_1
54 IO_L01N_1
53 IO_L01P_1
52
51 DONE
DS312-4 (v3.8) August 26, 2009
TMS
GND
IO_L06N_1/RHCLK7
IO_L06P_1/RHCLK6
IO_L05N_1/RHCLK5
IO_L05P_1/RHCLK4
GND
IO_L04N_1/RHCLK3
IO_L04P_1/RHCLK2
IO_L03N_1/RHCLK1
IO_L03P_1/RHCLK0
GND
VCCINT
GND
DS312-4_02_082009
Product Specification
R