M4A3-256/128-10YC LATTICE SEMICONDUCTOR, M4A3-256/128-10YC Datasheet - Page 17
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M4A3-256/128-10YC
Manufacturer Part Number
M4A3-256/128-10YC
Description
CPLD ispMACH™ 4A Family 10K Gates 256 Macro Cells 83.3MHz/118MHz EECMOS Technology 3.3V 208-Pin PQFP Tray
Manufacturer
LATTICE SEMICONDUCTOR
Datasheet
1.M4A5-6432-10JNC.pdf
(62 pages)
Specifications of M4A3-256/128-10YC
Package
208PQFP
Family Name
ispMACHÂ 4A
Device System Gates
10000
Number Of Macro Cells
256
Maximum Propagation Delay Time
10 ns
Number Of User I/os
128
Typical Operating Supply Voltage
3.3 V
Maximum Operating Frequency
83.3|118 MHz
Number Of Product Terms Per Macro
20
Operating Temperature
0 to 70 °C
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M4A3-256/128-10YC
Manufacturer:
LATTICE
Quantity:
368
Company:
Part Number:
M4A3-256/128-10YC
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
I/O Cell
The I/O cell (Figures 10 and 11) simply consists of a programmable output enable, a feedback path, and
flip-flop (except ispMACH 4A devices with 1:1 macrocell-I/O cell ratio). An individual output enable
product term is provided for each I/O cell. The feedback signal drives the input switch matrix.
The I/O cell (Figure 10) contains a flip-flop, which provides the capability for storing the input in a D-type
register or latch. The clock can be any of the PAL block clocks. Both the direct and registered versions of
the input are sent to the input switch matrix. This allows for such functions as “time-domain-multiplexed”
data comparison, where the first data value is stored, and then the second data value is put on the I/O pin
and compared with the previous stored value.
Note that the flip-flop used in the ispMACH 4A I/O cell is independent of the flip-flops in the macrocells.
It powers up to a logic low.
Zero-Hold-Time Input Register
The ispMACH 4A devices have a zero-hold-time (ZHT) fuse which controls the time delay associated with
loading data into all I/O cell registers and latches. When programmed, the ZHT fuse increases the data path
setup delays to input storage elements, matching equivalent delays in the clock path. When the fuse is erased,
the setup time to the input storage element is minimized. This feature facilitates doing worst-case designs
for which data is loaded from sources which have low (or zero) minimum output propagation delays from
clock edges.
Figure 10. I/O Cell for ispMACH 4A Devices with 2:1
Output Enable
Switch Matrix
Product Term
From Output
Individual
To Input
Switch
Matrix
Macrocell-I/O Cell Ratio
Q
D/L
Block CLK0
Block CLK1
Block CLK2
Block CLK3
Power-up reset
ispMACH 4A Family
17466G-017
Figure 11. I/O Cell for ispMACH 4A Devices with 1:1
Output Enable
Switch Matrix
Product Term
From Output
Individual
To Input
Switch
Matrix
Macrocell-I/O Cell Ratio
17466G-018
17