ISPLSI 1048EA-100LT128 LATTICE SEMICONDUCTOR, ISPLSI 1048EA-100LT128 Datasheet - Page 8

• Manufacturer Part Number: ISPLSI 1048EA-100LT128
• Description: CPLD ispLSI® 1000EA Family 8K Gates 192 Macro Cells 100MHz EECMOS Technology 5V 128-Pin TQFP
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of ISPLSI 1048EA-100LT128

• Package: 128TQFP
• Family Name: ispLSI® 1000EA
• Device System Gates: 8000
• Number Of Macro Cells: 192
• Maximum Propagation Delay Time: 12.5 ns
• Number Of User I/os: 96
• Number Of Logic Blocks/elements: 48
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 100 MHz
• Operating Temperature: 0 to 70 °C

1. Internal timing parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
Internal Timing Parameters
PARAMETER
Outputs
t
t
t
t
t
Clocks
t
t
t
t
t
Global Reset
t
ob
sl
oen
odis
goe
gy0
gy1/2
gcp
ioy2/3
iocp
gr
50 Output Buffer Delay
51 Output Slew Limited Delay Adder
52 I/O Cell OE to Output Enabled
53 I/O Cell OE to Output Disabled
54 Global OE
55 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
56 Clock Delay, Y1 or Y2 to Global GLB Clock Line
57 Clock Delay, Clock GLB to Global GLB Clock Line
58 Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line
59 Clock Delay, Clock GLB to I/O Cell Global Clock Line
60 Global Reset to GLB and I/O Registers
#
1
DESCRIPTION
8
Specifications ispLSI 1048EA
MIN. MAX.
0.9
0.9
0.8
0.0
0.8
—
—
—
—
—
—
-170
0.9
6.0
3.3
3.3
2.6
0.4
0.9
0.9
1.8
0.0
2.8
MIN. MAX.
1.1
0.9
0.8
0.0
0.8
—
—
—
—
—
—
-125
1.1
0.9
1.8
0.0
2.8
1.7
6.0
4.0
4.0
3.0
2.1
MIN. MAX.
1.9
1.5
0.8
0.0
0.8
—
—
—
—
—
—
-100
Table 2-0037A/1048EA
1.9
1.5
1.8
0.0
2.8
2.0
6.0
5.1
5.1
3.9
5.1
v.2.0
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns