ISPLSI 1048EA-100LT128 LATTICE SEMICONDUCTOR, ISPLSI 1048EA-100LT128 Datasheet
ISPLSI 1048EA-100LT128
Specifications of ISPLSI 1048EA-100LT128
Related parts for ISPLSI 1048EA-100LT128
ISPLSI 1048EA-100LT128 Summary of contents
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... I/O and open-drain output options. The basic unit of logic on the ispLSI 1048EA device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1…F7 (see Figure 1). There are a total of 48 GLBs in the ispLSI 1048EA device ...
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... Clocks in the ispLSI 1048EA device are selected using the Clock Distribution Network. Four dedicated clock pins (Y0, Y1, Y2 and Y3) are brought into the distribution network, and five clock outputs (CLK 0, CLK 1, CLK 2, IOCLK 0 and IOCLK 1) are provided to route clocks to the GLBs and I/O cells. The Clock Distribution Network can also be driven from a special clock GLB (D0) ...
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... BSCAN test Capture register hold time t btuco BSCAN test Update reg, falling edge of clock to valid output t btuoz BSCAN test Update reg, falling edge of clock to output disable t btuov BSCAN test Update reg, falling edge of clock to output enable Specifications ispLSI 1048EA T T btsu bth T btcl ...
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... IL V Input High Voltage IH o Capacitance (T =25 C, f=1.0 MHz) A SYMBOL PARAMETER C Dedicated Input, I/O, Y1, Y2, Y3, Clock Capacitance Clock Capacitance 2 Erase/Reprogram Specifications PARAMETER Erase/Reprogram Cycles Specifications ispLSI 1048EA 1 +1.0V CC +1.0V CC PARAMETER Commercial T = 0° 70° 3.3V TYPICAL 10 MINIMUM 10000 4 MIN. MAX. 4.75 5 ...
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... Maximum I varies widely with specific device configuration and operating frequency. Refer to the CC Power Consumption section of this data sheet and the Thermal Management section of the Lattice Semiconductor Data Book CD-ROM to estimate maximum I Specifications ispLSI 1048EA Figure 3. Test Load GND to 3.0V 1.5ns 1.5V 1 ...
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... Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock. 2. Refer to Timing Model in this data sheet for further details. 3. Standard 16-bit counter using GRP feedback. 4. Reference Switching Test Conditions section. Specifications ispLSI 1048EA Over Recommended Operating Conditions 1 DESCRIPTION ...
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... ORP Bypass Delay orpbp 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. Specifications ispLSI 1048EA 1 DESCRIPTION 3 7 -170 -125 -100 MIN ...
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... Clock Delay, Clock GLB to I/O Cell Global Clock Line Global Reset t 60 Global Reset to GLB and I/O Registers gr 1. Internal timing parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. Specifications ispLSI 1048EA 1 DESCRIPTION 8 -170 -125 -100 MIN ...
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... Clock (max) + Reg(clock-to-out) + Output gy0(max) + gco + = (#55 + #42 + #57) + (#42) + (#48 + #50) = (0.9 + 1.4 + 1.8) + (1.4) + (1.0 + 0.9) 7.4 1. Calculations are based upon timing specifications for the ispLSI 1048EA-170. Specifications ispLSI 1048EA GRP GLB #47 Feedback #34 Comb 4 PT Bypass GRP4 Reg 4 PT Bypass GLB Reg Bypass #30 ...
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... Product Terms Figure 4. Typical Device Power Consumption vs fmax Icc can be estimated for the ispLSI 1048EA using the following equation: Icc = 20mA + (# of PTs * .45 nets * Max Freq * .0087) Where PTs = Number of Product Terms used in design ...
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... TDI 20 TMS 46 TDO 50 TCK 78 RESET 17, 33, GND 97, 112 VCC 16, 48, 82, VCCIO 18 Specifications ispLSI 1048EA 24, 25, 26, Input/Output Pins - These are the general purpose I/O pins used by the 30, 31, 32, logic array. 37, 38, 39, 43, 44, 45, 55, 56, 57, 61, 62, 63, 69, 70, 71, 75, 76, 77, 88, 89, 90, 94, 95, ...
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... Pin Configuration ispLSI 1048EA 128-Pin PQFP Pinout Diagram GND I VCC 16 GND 17 VCCIO 18 RESET 19 TDI Specifications ispLSI 1048EA ispLSI 1048EA Top View I I/O 51 ...
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... Pin Configuration ispLSI 1048EA 128-Pin TQFP Pinout Diagram GND I VCC 16 GND 17 VCCIO 18 RESET 19 TDI I Specifications ispLSI 1048EA ispLSI 1048EA Top View I I/O 53 ...
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... XXXX COMMERCIAL ORDERING NUMBER 5.0 ispLSI 1048EA-170LQ128 5.0 ispLSI 1048EA-170LT128 7.5 ispLSI 1048EA-125LQ128 7.5 ispLSI 1048EA-125LT128 ispLSI 1048EA-100LQ128 10 10 ispLSI 1048EA-100LT128 14 X Grade Blank = Commercial Package Q128 = 128-Pin PQFP T128 = 128-Pin TQFP Power L = Low 0212/1048EA PACKAGE 128-Pin PQFP 128-Pin TQFP 128-Pin PQFP ...