M25P20-VMN6PB NUMONYX, M25P20-VMN6PB Datasheet - Page 21

• Manufacturer Part Number: M25P20-VMN6PB
• Description: Flash Mem Serial-SPI 3.3V 2M-Bit 256K x 8 8ns 8-Pin SO N Tray
• Manufacturer: NUMONYX

Specifications of M25P20-VMN6PB

• Package: 8SO N
• Cell Type: NOR
• Density: 2 Mb
• Architecture: Sectored
• Block Organization: Symmetrical
• Typical Operating Supply Voltage: 3.3 V
• Sector Size: 64KByte x 4
• Timing Type: Synchronous
• Operating Temperature: -40 to 85 °C
• Interface Type: Serial-SPI

6.4.3
6.4.4
BP1, BP0 bits
The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be
software protected against Program and Erase instructions. These bits are written with the
Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP1,
BP0) bits is set to 1, the relevant memory area (as defined in
against Page Program (PP) and Sector Erase (SE) instructions. The Block Protect (BP1,
BP0) bits can be written provided that the Hardware Protected mode has not been set. The
Bulk Erase (BE) instruction is executed if, and only if, both Block Protect (BP1, BP0) bits are
0.
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware Protected mode (when the Status Register
Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven Low). In this mode, the
non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the
Write Status Register (WRSR) instruction is no longer accepted for execution.
Figure 10. Read Status Register (RDSR) Instruction Sequence and Data-Out
S
C
D
Q
Sequence
0
High Impedance
1
2
Instruction
3
4
5
6
7
MSB
7
8
6
Status Register Out
9 10 11 12 13 14 15
5
4
3
2
1
0
MSB
7
Table
6
Status Register Out
5
2) becomes protected
4
3
2
1
0
7
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