MT48LC32M16A2P-75:C Micron Technology Inc, MT48LC32M16A2P-75:C Datasheet - Page 50

• Manufacturer Part Number: MT48LC32M16A2P-75:C
• Description: DRAM Chip SDRAM 512M-Bit 32Mx16 3.3V 54-Pin TSOP-II Tray
• Manufacturer: Micron Technology Inc
• Type: SDRAMr
• Series: -r

Specifications of MT48LC32M16A2P-75:C

• Density: 512 Mb
• Maximum Clock Rate: 133 MHz
• Package: 54TSOP-II
• Address Bus Width: 15 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Random Access Time: 6|5.4 ns
• Operating Temperature: 0 to 70 °C
• Organization: 32Mx16
• Address Bus: 15b
• Access Time (max): 6/5.4ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 115mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 512M (32Mx16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 54-TSOP (0.400", 10.16mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 34:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
DQML, DQMU
Power-Down Mode
COMMAND
Precharge all
BA0, BA1
A11, A12
active banks
A0–A9,
DQM/
CKE
CLK
A10
DQ
Note:
t CMS
High-Z
t CKS
t AS
SINGLE BANK
PRECHARGE
ALL BANKS
BANK(S)
T0
t CMH
t CKH
t AH
Violating refresh requirements during power-down may result in a loss of data.
Two clock cycles
All banks idle, enter
power-down mode
t CK
T1
NOP
t CKS
t CL
T2
NOP
Input buffers gated off while in
power-down mode
t CH
50
Exit power-down mode
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
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t CKS
Tn + 1
512Mb: x4, x8, x16 SDRAM
NOP
All banks idle
©2000 Micron Technology, Inc. All rights reserved.
Tn + 2
ACTIVE
ROW
ROW
BANK
Timing Diagrams
Don’t Care