MT48LC32M16A2P-75:C Micron Technology Inc, MT48LC32M16A2P-75:C Datasheet - Page 36

• Manufacturer Part Number: MT48LC32M16A2P-75:C
• Description: DRAM Chip SDRAM 512M-Bit 32Mx16 3.3V 54-Pin TSOP-II Tray
• Manufacturer: Micron Technology Inc
• Type: SDRAMr
• Series: -r

Specifications of MT48LC32M16A2P-75:C

• Density: 512 Mb
• Maximum Clock Rate: 133 MHz
• Package: 54TSOP-II
• Address Bus Width: 15 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Random Access Time: 6|5.4 ns
• Operating Temperature: 0 to 70 °C
• Organization: 32Mx16
• Address Bus: 15b
• Access Time (max): 6/5.4ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 115mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 512M (32Mx16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 54-TSOP (0.400", 10.16mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 29:
WRITE with Auto Precharge
Figure 30:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
READ with Auto Precharge Interrupted by a WRITE
WRITE with Auto Precharge Interrupted by a READ
Internal
States
Internal
States
Notes:
Note:
COMMAND
COMMAND
ADDRESS
ADDRESS
BANK m
BANK m
BANK n
BANK n
1. DQM is HIGH at T2 to prevent D
• Interrupted by a READ (with or without auto precharge): A READ to bank m will inter-
• Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will
DQM
CLK
CLK
rupt a WRITE on bank n when registered, with the data-out appearing CL later. The
PRECHARGE to bank n will begin after
to bank m is registered. The last valid WRITE to bank n will be data-in registered one
clock prior to the READ to bank m (see Figure 30).
interrupt a WRITE on bank n when registered. The PRECHARGE to bank n will begin
after
valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank
m (see Figure 31 on page 37).
DQ
DQ
DQM is LOW.
1
Active
Page
t
READ - AP
BANK n,
WR is met, where
Page Active
BANK n
COL a
T0
NOP
T0
READ with Burst of 4
WRITE - AP
BANK n,
Page Active
BANK n
Page Active
COL a
T1
D
T1
NOP
CL = 3 (BANK n)
a
IN
WRITE with Burst of 4
a + 1
T2
T2
D
NOP
NOP
IN
t
WR begins when the WRITE to bank m is registered. The last
36
BANK m,
READ - AP
T3
COL d
T3
BANK m
OUT
D
NOP
OUT
a
Interrupt Burst, Write-Back
t
WR - BANK n
READ with Burst of 4
- a + 1 from contending with D
Micron Technology, Inc., reserves the right to change products or specifications without notice.
BANK m,
WRITE - AP
COL d
T4
BANK m
CL = 3 (BANK m)
T4
D
NOP
d
t
IN
Interrupt Burst, Precharge
WR is met, where
WRITE with Burst of 4
Transitioning Data
Transitioning Data
T5
T5
d + 1
NOP
NOP
D
IN
Precharge
t
RP - BANK n
t
RP - BANK n
512Mb: x4, x8, x16 SDRAM
T6
T6
d + 2
D
NOP
NOP
D
OUT
d
IN
t
WR begins when the READ
©2000 Micron Technology, Inc. All rights reserved.
Don’t Care
Don’t Care
T7
T7
t WR - BANK m
d + 3
D
d + 1
NOP
NOP
D
OUT
IN
t RP - BANK m
IN
Write-Back
- d at T4.
Idle
Operations