MT48LC32M16A2P-75:C Micron Technology Inc, MT48LC32M16A2P-75:C Datasheet - Page 21

• Manufacturer Part Number: MT48LC32M16A2P-75:C
• Description: DRAM Chip SDRAM 512M-Bit 32Mx16 3.3V 54-Pin TSOP-II Tray
• Manufacturer: Micron Technology Inc
• Type: SDRAMr
• Series: -r

Specifications of MT48LC32M16A2P-75:C

• Density: 512 Mb
• Maximum Clock Rate: 133 MHz
• Package: 54TSOP-II
• Address Bus Width: 15 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Random Access Time: 6|5.4 ns
• Operating Temperature: 0 to 70 °C
• Organization: 32Mx16
• Address Bus: 15b
• Access Time (max): 6/5.4ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 115mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 512M (32Mx16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 54-TSOP (0.400", 10.16mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 8:
READs
Figure 9:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
Example Meeting
READ Command
COMMAND
READ bursts are initiated with a READ command, as shown in Figure 9.
The starting column and bank addresses are provided with the READ command, and
auto precharge either is enabled or disabled for that burst access. If auto precharge is
enabled, the row being accessed is precharged at the completion of the burst. For the
generic READ commands used in the following illustrations, auto precharge is disabled.
During READ bursts, the valid data-out element from the starting column address will
be available following CL after the READ command. Each subsequent data-out element
will be valid by the next positive clock edge. Figure 10 on page 22 shows general timing
for each possible CL setting.
A subsequent ACTIVE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The minimum
time interval between successive ACTIVE commands to different banks is defined by
t
A0–A9, A11, A12: x4
RRD.
A0–A9, A11: x8
CLK
A11, A12: x16
A0–A9: x16
BA0, BA1
t
A12: x8
RCD (MIN) when 2 <
RAS#
CAS#
WE#
A10
CLK
CKE
CS#
ACTIVE
T0
HIGH
DISABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
NOP
T1
ADDRESS
COLUMN
21
ADDRESS
BANK
t
RCD
t
RCD (MIN)/
Don't Care
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T2
NOP
t
CK ≤ 3
READ or
WRITE
512Mb: x4, x8, x16 SDRAM
T3
Don’t Care
©2000 Micron Technology, Inc. All rights reserved.
T4
Operations