MT48LC2M32B2P-7:G Micron Technology Inc, MT48LC2M32B2P-7:G Datasheet - Page 56

• Manufacturer Part Number: MT48LC2M32B2P-7:G
• Description: DRAM Chip SDRAM 64M-Bit 2Mx32 3.3V 86-Pin TSOP-II Tray
• Manufacturer: Micron Technology Inc
• Type: SDRAMr
• Series: -r

Specifications of MT48LC2M32B2P-7:G

• Density: 64 Mb
• Maximum Clock Rate: 143 MHz
• Package: 86TSOP-II
• Address Bus Width: 13 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Random Access Time: 17|8|5.5 ns
• Operating Temperature: 0 to 70 °C
• Organization: 2Mx32
• Address Bus: 13b
• Access Time (max): 17/8/5.5ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 160mA
• Pin Count: 86
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 64M (2Mx32)
• Speed: 143MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 86-TFSOP (0.400", 10.16mm Width)
• Lead Free Status / Rohs Status: Compliant

Figure 38:
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
64MSDRAMx32_2.fm - Rev. J 12/08 EN
Single READ
DQML, DQMH
COMMAND
BA0, BA1
Notes:
DQM /
A0-A9
CKE
A10
CLK
DQ
t CMS
t CKS
t AS
t AS
t AS
1. For this example, BL = 1, CL = 2, and the READ burst is followed by a “manual” PRECHARGE.
2. A8, A9 = “Don’t Care.”
ACTIVE
T0
ROW
ROW
BANK
t CKH
t CMH
t AH
t AH
t AH
t RCD
t RAS
t RC
t CK
T1
NOP
DISABLE AUTO PRECHARGE
t CMS
t CL
COLUMN m 2
T2
BANK
READ
t CH
t CMH
CAS Latency
56
SINGLE BANK
PRECHARGE
ALL BANKS
BANK
T3
t LZ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t RP
t AC
T4
NOP
D
OUT
t OH
t HZ
m
BANK
ROW
T5
ROW
ACTIVE
©2001 Micron Technology, Inc. All rights reserved.
64Mb: x32 SDRAM
DON’T CARE
UNDEFINED
Timing Diagrams