74LVC126APW-T NXP Semiconductors, 74LVC126APW-T Datasheet - Page 2

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74LVC126APW-T

Manufacturer Part Number
74LVC126APW-T
Description
Buffer/Line Driver 4-CH Non-Inverting 3-ST CMOS 14-Pin TSSOP T/R
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 74LVC126APW-T

Package
14TSSOP
Logic Family
LVC
Logic Function
Buffer/Line Driver
Number Of Outputs Per Chip
4
Output Type
3-State
Input Signal Type
Single-Ended
Maximum Propagation Delay Time @ Maximum Cl
2.7(Typ)@2.7V|2.4(Typ)@3.3V ns
Tolerant I/os
5 V
Typical Quiescent Current
0.1 uA
Polarity
Non-Inverting
Philips Semiconductors
4. Functional diagram
5. Pinning information
74LVC126A_6
Product data sheet
Fig 1. Logic symbol
Fig 3. Logic diagram
Fig 4. Pin configuration for SO14 and (T)SSOP14
GND
1OE
2OE
1A
1Y
2A
2Y
5.1 Pinning
10
12
13
1
2
3
4
5
6
7
2
1
5
4
9
1OE
2OE
3OE
4OE
1A
2A
3A
4A
126
001aac982
mna235
1Y
2Y
3Y
4Y
11
14
13
12
11
10
3
6
8
9
8
V
4OE
4A
4Y
3OE
3A
3Y
nOE
CC
nA
Rev. 06.00 — 16 May 2006
Quad buffer/line driver with 5 V tolerant input/outputs; 3-state
Fig 2. IEC logic symbol
Fig 5. Pin configuration for DHVQFN14
(1) * The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
mna234
index area
terminal 1
nY
2OE
1A
1Y
2A
2Y
10
12
13
2
1
5
4
9
Transparent top view
2
3
4
5
6
EN1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
GND
126
mna236
1
(1)
74LVC126A
13
12
11
10
11
9
3
6
8
001aac983
4OE
4A
4Y
3OE
3A
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