SI2493-C-FT Silicon Laboratories Inc, SI2493-C-FT Datasheet - Page 90

• Manufacturer Part Number: SI2493-C-FT
• Description: 56 KBPS, V.92 ISOMODEM SYSTEM-SIDE - LEAD-FREE TSSOP 0 TO 7
• Manufacturer: Silicon Laboratories Inc

Specifications of SI2493-C-FT

• Mfg Application Notes: SI2493/57/34/15/04, Appl Note AN93
• Data Format: V.21, V.22, V.23, V.29, V.32, V.34, V.90, V.92, Bell 103, Bell 212A
• Baud Rates: 56k
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AN93
3.3.37. U6E (CK1)
U6E controls the clockout divider. Bits 15:13 and 7:0 are
reserved. U6E resets to 0x7F20 with a power-on or
manual reset. (See Table 58.)
Bits[12:8] (R1) make up the R1 clockout divider. An
81.92 MHz (Si2404/15) or 98.304 MHz (Si2434/57)
clock signal passes through a ÷(R
the CLKOUT signal on pin 3 of the Si2493/57/34/15/04.
If R1 = 00000
default
CLKOUT = 2.048 MHz
CLKOUT = 2.048 MHz
adjustment
40.96 MHz for the Si2404/Si2415 and 3.17 MHz to
49.152 MHz for the Si2434/Si2457/Si2493.
3.3.39. U70 (IO0)
U70 controls escape and several indicator and detector
masks and provides several read-only status bits. (See
Table 60.) Bits 5, 6, 7, and 14 are reserved.
Bits 4:0 are read only, and bits 15 and 13:8 are read/
write. U70 resets to 0x2700 with a power-on or manual
reset.
Bit 15 (HES) = 0
escape pin (Si2493/57/34/15/04, pin 22 [ESC]).
90
15:13
15:8
12:8
15:8
Bit
Bit
7:0
7:0
Bit
7:0
Reserved Do not modify
Reserved
Reserved
Reserved
LVS[7:0]
Name
PTMR
Name
Name
value
R1
range
b
, CLKOUT is disabled. R1 is set at a
b
Parallel Port Receive FIFO Interrupt Timer. PTMR (msec units)
(default) disables the hardware
Function
Line Voltage Status.
Eight bit signed 2s complement number representing the on-hook and off-hook tip-ring voltage. Each bit
represents 1 V. Polarity of the voltage is represented by the MSB (sign bit). 0000_0000 = Measured volt-
age is < 3 V.
Read returns zero.
Function
Do not modify.
R1 CLKOUT Divider.
Read returns zero. (bit 5 returns 1) Do not modify.
(1 < R1 < 30)
of
(Si2404/15).
11111
(Si2434/57)
b
1
+1) circuit to derive
is
The
resulting
2.64 MHz
Table 57. U6C Bit Map
Table 58. U6E Bit Map
Table 59. U6F Bit Map
CLKOUT
Rev. 0.9
or
to
in
3.3.38. U6F (PTME)
U6F contains the parallel port receive FIFO interrupt
timer and resets to 0x00FF.
Bits [15:8] are reserved and should not be written to any
value other than 0b.
Bits[7:0] set the period of an internal timer that is reset
whenever the parallel port receive FIFO (Parallel
Interface 0 register) is read. If the internal timer expires
with data in the RX FIFO, an interrupt is generated
regardless of the state of RXF (Parallel Interface 1
register, bit 7). This ensures that the host always
removes all receive data from the parallel port receive
FIFO even if RXF is not set.
Setting HES = 1
escape from the data mode to the command mode
occurs at the rising edge of the ESC pin. Multiple
escape options can be enabled simultaneously.
For example, U70[13] (TES) = 1
enables the “+++” escape. If HES is also set
(HES = 1
the 9th bit escape can also be enabled with the AT\B6
command or through autobaud.
Function
b
), either escape method works. Additionally,
b
enables ESC. When ESC is enabled,
b
by default, which