SI2493-C-FT Silicon Laboratories Inc, SI2493-C-FT Datasheet - Page 154

• Manufacturer Part Number: SI2493-C-FT
• Description: 56 KBPS, V.92 ISOMODEM SYSTEM-SIDE - LEAD-FREE TSSOP 0 TO 7
• Manufacturer: Silicon Laboratories Inc

Specifications of SI2493-C-FT

• Mfg Application Notes: SI2493/57/34/15/04, Appl Note AN93
• Data Format: V.21, V.22, V.23, V.29, V.32, V.34, V.90, V.92, Bell 103, Bell 212A
• Baud Rates: 56k
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AN93
Si2493/57/34/15/04 Layout Check List
Table 101 is a checklist that the designer can use during the layout process to ensure that all the recommendations
in this application note have been implemented. Additionally, Figure 28 provides an annotated diagram of all
relevant layout guidelines for the SI3054 CNR/AMR/ACR applications. See "3.5.19.4. Safety" on page 137 for
information about safety testing and the use of a fuse.
154
P
10
12
13
14
11
#
1
2
3
4
5
6
7
8
9
U1 and U2 are placed so that pins 9–16 of U1 are facing pins 1–8 of U2. C1 and C2 are
placed directly between U1 and U2.
Place U1, U2, C1, and C2 so that the recommended minimum creepage spacing for the
target application is implemented. R12 and R13 should be close to U1.
C1 and C2 should be placed directly between U1 and U2. Short, direct traces should be
used to connect C1 and C2 to U1 and U2. These traces should never be longer than two
inches and should be minimized in length. Place C2 such that its accompanying trace to
the C2B pin (pin 6) on the Si3018 is not close to the trace from R7 to the RNG1 pin on
the Si3018 (pin 8).
Place R7 and R8 as close as possible to the RNG1 and RNG2 pins (pins 8 and 9),
ensuring a minimum trace length from the RNG1 or RNG2 pin to the R7 or R8 resistor. In
order to space the R7 component further from the trace from C2 to the C2B pin, it is
acceptable to orient it 90 degrees relative to the RNG1 pin (pin 8).
The area of the loop from C50 to U1 pin 4 and from C51 to pin 13 back to pin 12 (DGND)
should be minimized. The return traces to U2 pin 12 (DGND) should be on the compo-
nent side.
The loop formed by XTALI, Y1, and XTALO should be minimized and routed on one
layer. The loop formed by Y1, C40, and C41 should be minimized and routed on one
layer.
The digital ground plane is made as small as possible, and the ground plane has
rounded corners.
Series resistors on clock signals are placed near source.
Use a minimum of 15 mil width traces in DAA section, use a minimum of 20 mil width
traces for IGND.
C3 should be placed across the diode bridge, and the area of the loop formed from
Si3018/19 pin 11 through C3 to the diode bridge and back to Si3018/19 pin 15 should be
minimized.
FB1, FB2, and RV1 should be placed as close as possible to the RJ11.
C8 and C9 should be placed so that there is a minimal distance between the nodes
where they connect to chassis ground.
Use at least a 20 mil wide trace from RJ11 to FB1, FB2, RV1, C8, C9, and F1.
The routing from TIP and RING of the RJ11 through F1 to the ferrite beads should be
well-matched.
Table 101. Layout Check List
Layout Items
Rev. 0.9
Required