S19233PBIFB AMCC, S19233PBIFB Datasheet - Page 8

• Manufacturer Part Number: S19233PBIFB
• Description: Ethernet/Fibre Channel 49-Pin BGA
• Manufacturer: AMCC

Specifications of S19233PBIFB

• Package: 49BGA
• Maximum Data Rate: 11.32 Gbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 380 mA
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.65|3.03 V
• Maximum Operating Supply Voltage: 1.95|3.56 V

S19233 – 10 G Ethernet/Fibre Channel/SONET/SDH
Dual CDR
RECEIVE OPTICAL SIDE – DESCRIPTION
The receive side of the S19233 dual CDR device pro-
vides an important EDC function to compensate
chromatic dispersion for 10 Gigabit Ethernet/10 G
Fibre Channel/SONET STS-192 transmitted over sin-
gle mode fiber. It reshapes the received signal
waveform and amplifies the signal to an optimal signal
level so that the receive side CDR can achieve opti-
mum performance.
Analog Front End
An AGC gain stage with offset adjust capability is at
the first input stage. The S19233 AGC stage takes the
differential serial data from the RXDATINP/N pins.
There is a center-tap pin, RXCTAP, that provides a
flexible solution for a single-ended input configuration.
The input to this stage must be AC coupled.
Clock Data Recovery
Clock Data recovery (CDR), as shown in the block dia-
gram in Figure 2, S19233 Dual CDR Block Diagram,
recovers a clock that is the same frequency as the
incoming data bit rate at the serial data input. The
clock is phase aligned by a Phase Lock Loop (PLL) so
that it samples the data in the center of the data eye
pattern.
The Clock Data Recovery Unit (CDR) extracts a syn-
chronous signal from the serial data input using a PLL.
The PLL consists of a Voltage Controlled Oscillator
(VCO), Phase/Frequency Detectors (PFD), and a loop
filter.
The frequency detector ensures predictable lock-up
conditions. It is used during acquisition and serves as
a means to pull the VCO into the range of the data rate
where the phase detector is capable of acquiring lock.
The phase detector used in the CDR is designed to
give minimum static phase error of the PLL. When a
transition has occurred, the value of the sample in the
vicinity of the transition indicates whether the VCO
clock leads or lags the incoming data, and the phase
detector produces a binary output accordingly.
When a loss of signal condition exists, the PLL locks
onto the reference clock (REFCLKP/N) to provide a
steady output clock. The output data is invalid and can
be squelched.
8
The phase relationship between the edge transitions
of the data and those of the generated clock are com-
pared by a phase/frequency discriminator. Output
pulses from the discriminator indicate the required
direction of phase corrections. These pulses are
smoothed by an integral loop filter (LF). The output of
the loop filter controls the frequency of the Voltage
Controlled Oscillator (VCO), which generates the
recovered clock.
Frequency stability without incoming data is guaran-
teed by the reference input (REFCLKP/N) onto which
the PLL locks when data is lost. If the frequency of the
incoming signal varies by a value greater than that
stated in Table 13, with respect to REFCLKP/N, the
PLL will be declared out of lock, and the PLL will lock
to the reference clock.
The loop filter transfer function is optimized in order to
enable the PLL to track the jitter yet tolerate the mini-
mum transition density expected in a received 10
Gigabit Ethernet, 10 G Fiber Channel and SONET
data signal. There are two pins (RXCAP1 and
RXCAP2) to connect the external capacitor and resis-
tors in order to adjust the PLL loop performance.
The total loop dynamics of the clock recovery PLL
yield a jitter tolerance which exceeds the minimum tol-
erance proposed for SONET equipment by the
Telcordia standard.
Receive Signal Lock Detect
The S19233 contains a lock detect circuit that moni-
tors the integrity of the serial data inputs. If the
received serial data fails the frequency test as
describe previously, the PLL will be forced to lock to
the local reference clock. This will maintain the correct
frequency of the recovered clock output under loss-of-
signal or loss-of-lock conditions. If the recovered clock
frequency deviates from the local reference clock fre-
quency by more than the typical value stated in Table
13, Performance Specifications, the PLL will be
declared out of lock. The lock detect circuit will poll the
input data stream in an attempt to reacquire lock to
data. If the recovered clock frequency is determined to
be within the typical value stated in Table 13, Perfor-
mance Specifications, the PLL will be declared in lock
and the lock detect output will go active. An inactive
Signal Detect (SD) setting will also cause an out-of-
lock condition.
Revision 5.00 – March 16, 2007
AMCC Confidential and Proprietary
Data Sheet