S19233PBIFB AMCC, S19233PBIFB Datasheet - Page 15
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S19233PBIFB
Manufacturer Part Number
S19233PBIFB
Description
Ethernet/Fibre Channel 49-Pin BGA
Manufacturer
AMCC
Datasheet
1.S19233PBIFB.pdf
(39 pages)
Specifications of S19233PBIFB
Package
49BGA
Maximum Data Rate
11.32 Gbps
Transmission Media Type
Wire
Power Supply Type
Analog
Typical Supply Current
380 mA
Typical Operating Supply Voltage
1.8|3.3 V
Minimum Operating Supply Voltage
1.65|3.03 V
Maximum Operating Supply Voltage
1.95|3.56 V
S19233 – 10 G Ethernet/Fibre Channel/SONET/SDH
Dual CDR
SONET Jitter Generation
The following jitter generation requirement applies to
STS-192 interfaces as defined in GR-253-CORE.
According to GR-253-CORE, jitter generation shall
not exceed 0.10 UI
measured using a bandpass measurement filter
with a high-pass cutoff frequency of 50 kHz and a
low-pass cutoff frequency of at least B3 = 80 MHz.
Note that for SONET rates up to STS-48, the current
jitter generation requirement in GR-253-CORE states
that the generated jitter must be less than 0.01 UI
and 0.10 UI
of RMS phase variations with less than 0.01 UI granu-
larity (1 picosecond) may not be feasible. Therefore,
this requirement specifies the jitter generation only in
terms of 0.10 UI
The S19233 exceeds the Telcordia Jitter Generation
Specification by having less than 50% of the budget in
normal modes of operation.
10 Gigabit Ethernet Jitter Tolerance
The following 10 Gigabit Ethernet jitter tolerance
requirement applies to 10GBASE-ER as defined in
IEEE Std 802.3ae. This total jitter is composed of three
components: deterministic jitter; random jitter; and an
additional sinusoidal jitter.
The three fundamental components of Jitter Tolerance
testing are:
Input Jitter (amount of Dj and Rj)
Dj: 0.35 UI
Rj: 0.015 UI
The random jitter (Rj) component of the input signal
has uniform spectral content over the measurement
frequency range of at least 1 MHz to 1 GHz. Input Sig-
nal must pass the bathtub curves between BERs of
10
AMCC Confidential and Proprietary
-6
•
•
•
and 10
Input Jitter (Dj and Rj)
Sinusoidal Jitter
Test Pattern (Test patterns are different for
10GBASE-R and 10GBASE-W)
pp
-12
PP
rms
. At the STS-192 rate, the measurement
as shown in Figure 5.
PP
.
PP
for STS-192 interfaces when
rms
Sinusoidal Jitter
The Sj applied for tolerance testing is defined by the
jitter mask shown in Figure 6 and Table 6 (per section
IEEE Std 802.3ae). The Loop Bandwidth (LB) for
S19233 is approximately 8 MHz.
Test Pattern
Test pattern is chosen per IEEE Std 802.3ae Section
52.9.1. The test pattern is a static pattern and can be
loaded into a BERT. IEEE Std 802.3ae specifies two
pseudo-random test patterns for 10GBASE-ER test-
ing. One pattern represents typical scrambled data
while the other represents a less typical pattern which
could happen by chance and is thought to be more
demanding of the transmission process including the
clock recovery sub-system. Both patterns are bal-
anced over their length of 33792 bits.
Test pattern is constructed from 4 Segments
•
•
•
•
•
1 segment is constructed with 128 Blocks
1 block is 2 Sync Bits and 64 Payload Bits
Pay load bits are generated with the scrambler
shown in Figure 7.
Scrambler seeded per Table 7 and Table 8.
Data input is set to 1 or 0.
Revision 5.00 – March 16, 2007
Data Sheet
15