92HD89B2X5NDGXZBX Integrated Device Technology (Idt), 92HD89B2X5NDGXZBX Datasheet - Page 63

• Manufacturer Part Number: 92HD89B2X5NDGXZBX
• Description: Audio Codec 2ADC / 2DAC 24-Bit 40-Pin VFQFPN Tray
• Manufacturer: Integrated Device Technology (Idt)
• Type: PCMr

Specifications of 92HD89B2X5NDGXZBX

• Package: 40VFQFPN
• Adc/dac Resolution: 24 Bit
• Number Of Channels: 2ADC /2 DAC
• Sampling Rate: 192 KSPS
• Number Of Adc Inputs: 10
• Number Of Dac Outputs: 11
• Number Of Dacs: 2
• Operating Supply Voltage: 1.5|3.3|5 V

92HD89B
Four channel HD Audio codec optimized for low power
©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
Field Name
W2
W1
W0
Field Name
Rsvd
EnMask4
EnMask3
Reg
Get
Set
7.4.15. AFG (NID = 01h): GPIOUnsol
Byte 4 (Bits 31:24)
Bits
Wake enable for GPIO3: 0 = wake-up event is disabled; 1 = When HD Audio
link is powered down (RST# is asserted), a wake-up event will trigger a Status
Change Request event on the link.
2
Wake enable for GPIO2: 0 = wake-up event is disabled; 1 = When HD Audio
link is powered down (RST# is asserted), a wake-up event will trigger a Status
Change Request event on the link.
1
Wake enable for GPIO1: 0 = wake-up event is disabled; 1 = When HD Audio
link is powered down (RST# is asserted), a wake-up event will trigger a Status
Change Request event on the link.
0
Wake enable for GPIO0: 0 = wake-up event is disabled; 1 = When HD Audio
link is powered down (RST# is asserted), a wake-up event will trigger a Status
Change Request event on the link.
Bits
31:3
Reserved.
4
Unsolicited enable mask for GPIO4. If set, and the Unsolicited Response con-
trol for this widget has been enabled, an unsolicited response will be sent when
GPIO2 is configured as input and changes state.
3
Unsolicited enable mask for GPIO3. If set, and the Unsolicited Response con-
trol for this widget has been enabled, an unsolicited response will be sent when
GPIO2 is configured as input and changes state.
Byte 3 (Bits 23:16)
R/W
RW
RW
RW
R/W
R
RW
RW
F1900h
Default
0h
0h
0h
Default
00000000h
0h
0h
63
Byte 2 (Bits 15:8)
Reset
POR - DAFG - ULR
POR - DAFG - ULR
POR - DAFG - ULR
Reset
N/A (Hard-coded)
POR - DAFG - ULR
POR - DAFG - ULR
Byte 1 (Bits 7:0)
719h
V 1.0 11/10
92HD89B