TMC2074-NE SMSC, TMC2074-NE Datasheet - Page 76

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TMC2074-NE

Manufacturer Part Number
TMC2074-NE
Description
Network Controller & Processor ICs Standalone Mode CircLink Cntlr
Manufacturer
SMSC
Datasheet

Specifications of TMC2074-NE

Product
Controller Area Network (CAN)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
NOTE:
NOTE:
Revision 0.2 (10-23-08)
COMR4 Register: Data Register
(1) 16 Bit Mode (W16=H)
(2) 8 Bit Mode and Word Mode=ON (W16=L, WDMD=1)
(3) 8 Bit Mode and Word Mode=Off (W16=L, WDMD=0)
To preserve the upper and lower bytes of word data in the same packet, COMR4 must be accessed in the
order of 08h access → 09h access.
(access in the order of 09h → 08h, 08h → 08h, or 09h → 09h will not preserve this data). This restriction
The upper/lower relationship is selected by the nSWAP pin.
*1 Not equivalent to the ARCNET original specifications.
- When reading/writing: ARCNET Data register(New)
Writing/ reading out the address in the 1 kByte RAM is indicated by the page register and intra-page
address register. Data access to packet buffer is performed via the data register.
Reading/writing is set by the RDDATA bit of COMR2.
Data can be accessed using settings in the RDDATA register only. For example, data register writing with
RDDATA = 1 setting, or data register reading with RDDATA = 0 setting will not normally be completed.
applies to both reading and writing.
*1
*1
*1
*1
COMR4
[READ/WRITE]
COMR4
[READ/WRITE]
COMR4
[READ/WRITE]
15-0
15-8
15-8
7-0
7-0
bit
bit
bit
(Data Register)
Name
RAMDT15-0
(Data Register)
name
RAMDT15-8
RAMDT7-0
(Data Register)
Name
--------
RAMDT7-0
DATASHEET
init. Value description
init. Value Description
init. value
X
X
X
X
0
Page 76
RAM Data 15-0
Description
RAM Data 15-8
RAM Data 7-0
Reserved (all "0")
RAM Data 7-0
address:08h or 09h
address:08h/09h
Dual Mode CircLink™ Controller
address:08h
SMSC TMC2074
Datasheet

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