E-STE10/100A STMicroelectronics, E-STE10/100A Datasheet - Page 68

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E-STE10/100A

Manufacturer Part Number
E-STE10/100A
Description
Telecom ICs PCI Ethernet Contlr
Manufacturer
STMicroelectronics
Datasheet

Specifications of E-STE10/100A

Mounting Style
SMD/SMT
Package / Case
PQFP-128
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Registers and descriptors description
4.4.2
68/82
Table 13.
Table 14.
Transmit descriptor
TDSE0
TDES1
TDES0
TDES1
TDSE2
TDSE3
30-24
23-22
21-16
13-12
Bit#
6-3
31
15
14
11
10
31
30
9
8
7
2
1
0
Own
Receive descriptor table
Transmit descriptor description
Name
31
OWN
-----
-----
UR
NC
CC
ES
TO
LO
EC
HF
UF
DE
LC
LS
---
---
IC
---
Own bit
1: Indicates this descriptor is ready to transmit
0: No transmit data in this descriptor.
Reserved
Under-run count
Reserved
Error summary. Logical OR of the following bits:
Transmit jabber time-out
Reserved
Loss of carrier
No carrier
Late collision
Excessive collision
Heartbeat fail
Collision count
Reserved
Under-run error
Deferred
Interrupt completed
Last descriptor
1: under-run error
8: excessive collision
9: late collision
10: no carrier
11: loss carrier
14: jabber time-out
Control
Buffer1 address
Buffer2 address
Buffer2 byte-count
Description
Status
Buffer1 byte-count
STE10/100A
0

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