LAN89218AQ_samples SMSC, LAN89218AQ_samples Datasheet - Page 84

• Manufacturer Part Number: LAN89218AQ_samples
• Description: Ethernet ICs High Perform Chip 10/100 NonPCI Cntrl
• Manufacturer: SMSC

Specifications of LAN89218AQ_samples

• Ethernet Connection Type: 10BASE-T, 100BASE-TX
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE802.3, IEEE802.3u
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 1.3 (02-23-10)
5.2.2
5.3
BASE ADDRESS
+ OFFSET
5Ch
6Ch
7Ch
8Ch
9Ch
50h
54h
58h
60h
64h
68h
70h
74h
78h
80h
84h
88h
90h
94h
98h
TX FIFO Ports
The TX Data Path consists of two FIFOs, TX Status and RX Data. The TX Status FIFO also has two
ports at different locations. When the TX Status FIFO Port is read, the top of the TX Status FIFO is
popped. When the TX Status FIFO PEEK Port is read, the top of the TX Status FIFO is not popped.
The TX data FIFO is Write Only. It is aliased to 8 DWORD (in 32-bit mode) or 16 DWORD locations
(in 16-bit mode). The host may access the top of the TX Data FIFO through any of these locations.
Table 5.1, "Direct Address Register
bus.
System Control and Status Registers
WORD_SWAP
RX_FIFO_INF
TX_FIFO_INF
RX_DP_CTL
BYTE_TEST
RESERVED
RESERVED
FREE_RUN
PMT_CTRL
GPIO_CFG
GPT_CFG
GPT_CNT
IRQ_CFG
FIFO_INT
HW_CFG
SYMBOL
INT_STS
RX_CFG
TX_CFG
ID_REV
INT_EN
Table 5.1 Direct Address Register Map
CONTROL AND STATUS REGISTERS
High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications
DATASHEET
Map", lists the registers that are directly addressable by the host
Chip ID and Revision.
Main Interrupt Configuration
Interrupt Status
Interrupt Enable Register
Reserved for future use
Read-only byte order testing register
FIFO Level Interrupts
Receive Configuration
Transmit Configuration
Hardware Configuration
RX Datapath Control
Receive FIFO Information
Transmit FIFO Information
Power Management Control
General Purpose IO Configuration
General Purpose Timer Configuration
General Purpose Timer Count
Reserved for future use
WORD SWAP Register
Free Run Counter
84
REGISTER NAME
See Page 85.
0000FFFFh
0000FFFFh
SMSC LAN89218
00000000h
00000000h
00000000h
87654321h
48000000h
00000000h
00000000h
00050000h
00000000h
00000000h
00001200h
00000000h
00000000h
00000000h
DEFAULT
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-
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Datasheet