LAN89218AQ_samples SMSC, LAN89218AQ_samples Datasheet - Page 53

• Manufacturer Part Number: LAN89218AQ_samples
• Description: Ethernet ICs High Perform Chip 10/100 NonPCI Cntrl
• Manufacturer: SMSC

Specifications of LAN89218AQ_samples

• Ethernet Connection Type: 10BASE-T, 100BASE-TX
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE802.3, IEEE802.3u
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications
Datasheet
IMPORTANT NOTE:
APPLICATION NOTE: Following deassertion of a power-on reset, the READY bit in PMT_CTRL will be set (high -
APPLICATION NOTE: In order for valid device configuration strap inputs to be read at power-on, the configuration
IMPORTANT NOTE:
APPLICATION NOTE: Following deassertion of a hardware reset, the READY bit in PMT_CTRL will be set (high -
APPLICATION NOTE: Following deassertion of a soft reset, the READY bit in PMT_CTRL will be set (high -”1”)
SMSC LAN89218
3.11.1
3.11.2
3.11.3
Power-On Reset (POR)
A Power-On reset occurs whenever power is initially applied to the LAN89218, or if power is removed
and reapplied to the LAN89218. A timer within the LAN89218 will assert the internal reset for a
maximum of 25 ms after the supply voltage reaches the minimum operational voltage. The READY bit
in the PMT_CTRL register can be read from the host interface and will read back a ‘0’ until the POR
is complete. Upon completion of the POR, the READY bit in PMT_CTRL is set high, and the LAN89218
can be configured via its control registers. Refer to
for details on the operational supply voltage range.
Hardware Reset Input (nRESET)
A hardware reset will occur when the nRESET input signal is driven low. The READY bit in the
PMT_CTRL register can be read from the host interface, and will read back a ‘0’ until the hardware
reset is complete. Upon completion of the hardware reset, the READY bit in PMT_CTRL is set high.
After the “READY” bit is set, the LAN89218 can be configured via its control registers. The nRESET
signal is pulled-high internally by the LAN89218 and can be left unconnected if unused. If used,
nRESET must be driven low for a minimum period as defined in
page
Soft Reset (SRST)
Soft reset is initiated by writing a ‘1’ to bit 0 of the HW_CFG register (SRST). This self-clearing bit will
return to ‘0’ after approximately 2 μs, at which time the Soft Reset is complete. Soft reset does not
clear control register bits marked as NASR.
143.
While the internal power-on reset circuit may assert during brown-out conditions, this is not
guaranteed. For proper operation in applications where brown-outs may occur, use of an
external reset circuit is recommended.
”1”) within 25 ms. If the software driver polls this bit and it is not set within 100ms, then an
error condition occurred.
strap input voltage levels must be stable and ready to be read (latched) within 15 ms (typical)
of the deassertion of POR reset. Device configuration straps are also latched as a result of
nRESET assertion. Refer to
"Detailed Reset Description," on page 52
For proper operation in applications where brown-outs may occur, use of an external reset
circuit is recommended.
”1”) immediately. If the software driver polls this bit and it is not set within 100 ms, then an
error condition occurred.
within 2 μs. If the software driver polls this bit and it is not set within 100 ms, then an error
condition occurred.
DATASHEET
Section 6.8, "nRESET Timing," on page 143
53
Section 7.2, "Operating Conditions**," on page 145
for additional details.
Section 6.8, "nRESET Timing," on
Revision 1.3 (02-23-10)
and
Section 3.11,