CS61584A-IL3 Cirrus Logic Inc, CS61584A-IL3 Datasheet - Page 42

• Manufacturer Part Number: CS61584A-IL3
• Description: Network Controller & Processor ICs IC 3.3V/5V Dul T1/E1 Line Intrfc Unit
• Manufacturer: Cirrus Logic Inc

Specifications of CS61584A-IL3

• Product: Framer
• Number Of Transceivers: 2
• Data Rate: 2.048 Mbps
• Supply Voltage (max): 3.465 V, 5.25 V
• Supply Voltage (min): 3.135 V, 4.75 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: PLCC-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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REFCLK - External Reference Clock Input (PLCC pin 36; TQFP pin 26)
XTALOUT - Crystal Oscillator Output (PLCC pin 37; TQFP pin 27)
Control
ATTEN0, ATTEN1 - Attenuator Select [Hardware Mode] (PLCC pins 25, 8; TQFP pins 16, 64)
CLKE - Clock Edge [Hardware mode] (PLCC pin 44; TQFP pin 33)
CON01, CON11 - Configuration Selection for Channel 1 [Hardware Mode]
CON21, CON31 - (PLCC pins 2, 65, 63, 61; TQFP pins 58, 53, 51, 49)
CON02, CON12 - Configuration Selection for Channel 2 [Hardware Mode]
CON22, CON32 - (PLCC pins 66, 64, 62, 52; TQFP pins 54, 52, 50, 41)
LLOOP - Local Loopback [Hardware Mode] (PLCC pin 5; TQFP pin 61)
MODE - Mode Select (PLCC pin 31; TQFP pin 21)
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Input reference clock for the receive and jitter attenuator circuits. When 1XCLK is high, REFCLK must
be a 1X clock (i.e., 1.544 MHz ±100 ppm for T1 applications or 2.048 MHz ±100 ppm for E1
applications). When 1XCLK is set low, REFCLK must be an 8X clock (i.e., 12.352 MHz ±100 ppm for T1
applications or 16.384 MHz ±100 ppm for E1 applications). The REFCLK input also determines the
transmission rate when TAOS is asserted.
A quartz crystal with a resonant frequency of 12.352 MHz for T1 applications or 16.384 MHz for E1
applications may be connected across the XTALOUT and REFCLK pins instead of using a CMOS
compatible clock source. The 1XCLK pin must be set low to select 8X clock operation. This pin must
remain unconnected if a quartz crystal is not used.
Selects the jitter attenuator path and -3 dB knee point for both channels (transmit/receive/neither). See
Table 3.
Controls the polarity of the recovered clock RCLK. When CLKE is high, RPOS and RNEG (or RDATA)
are valid on the falling edge of RCLK. When CLKE is low, RPOS and RNEG (or RDATA) are valid on
the rising edge of RCLK.
These pins configure the transmitter (pulse shape, pulse width, pulse amplitude, and driver impedance),
receiver (slicing level), coder (HDB3 vs B8ZS), and driver tristate. The CONx1 pins control channel 1
and the CONx2 pins control channel 2. Both channels must be configured to operate at the same data
rate on the line interface (both T1 or both E1). The arbitrary waveform options are not available during
Hardware mode operation. See Table 1.
A local loopback #2 of both channels is enabled when LLOOP is high. Selecting LLOOP causes the
TCLK, TPOS/TNEG (TDATA) inputs to be looped back through the transmitter, receiver and jitter
attenuator (if enabled) to the RCLK, RPOS/RNEG (RDATA) outputs. The data at TPOS/TNEG (TDATA)
continues to be transmitted to the line interface unless overridden by a TAOS request. The input on
RTIP and RRING is ignored.
When the RLOOP and TAOS pins are both high, the TCLK, TPOS/TNEG (TDATA) inputs are looped
back (local loopback #1) through the jitter attenuator (if enabled) to the RCLK, RPOS/RNEG (RDATA)
outputs for the selected channel. The data at TPOS/TNEG (TDATA) is also overridden with an all-ones
pattern (TAOS). The receive input at RTIP and RRING is ignored.
Hardware mode operation is selected when MODE is low, enabling the device to be configured and
monitored using control pins. Host mode operation is selected when MODE is high, enabling the device
to be configured and monitored over a microprocessor interface using the internal register set.
DS261PP5
CS61584A
CS61584A
DS261PP5
DS261F1