DS3154 Maxim Integrated Products, DS3154 Datasheet - Page 28

• Manufacturer Part Number: DS3154
• Description: Network Controller & Processor ICs Quad DS3-E3-STS-1 Li ne Interface Unit ST
• Manufacturer: Maxim Integrated Products

Specifications of DS3154

• Product: Framer
• Number Of Transceivers: 4
• Data Rate: 51.840 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 400 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TE-CSBGA

Figure 7-2. DS3 AIS Structure
M1 Subframe
M2 Subframe
M3 Subframe
M4 Subframe
M5 Subframe
M6 Subframe
M7 Subframe
Note 1: X1 is transmitted first.
Note 2: The 84 info bits contain the repetitive sequence 1010…, where the first 1 in the sequence immediately follows each X, P, F, C, or M bit.
8. DIAGNOSTICS
PRBS Generator and Detector. Each LIU has built-in pseudorandom bit sequence (PRBS) generator and detector
circuitry for physical layer testing. The device generates and detects unframed 2
PRBS, according to the ITU O.151 specification. To transmit a PRBS pattern, pull the TDSA and TDSB pins high
(hardware mode) or set configuration bits TDSA and TDSB (CPU bus mode). As
generator automatically generates 2
The PRBS detector, which is always enabled
and CPU bus modes) or through the PRBS and PBER status bits (CPU bus mode). When the PRBS detector is out
of synchronization, the PRBS pin is forced high. When the detector syncs to an incoming PRBS pattern, the PRBS
pin is driven low, then pulses high, synchronous with RCLK, for each bit error detected. See
8-2
set to zero when the detector syncs to an incoming PRBS pattern. A change of state of the PRBS bit can cause an
interrupt on the INT pin if the PRBSIE interrupt-enable bit is set to one. A pattern bit error can also cause an
interrupt if the PBERIE interrupt-enable bit is set to one. The PRBS detector also declares sync in the presence of
an incoming all-ones pattern.
X1
(1)
X2
(1)
P1
(0)
P2
(0)
M1
(0)
M2
(1)
M3
(0)
for details. In CPU bus mode, the PRBS status bit is set to one when the detector is out of synchronization and
84
Info
Bits
84
Info
Bits
84
Info
Bits
84
Info
Bits
84
Info
Bits
84
Info
Bits
84
Info
Bits
F1
(1)
F1
(1)
F1
(1)
F1
(1)
F1
(1)
F1
(1)
F1
(1)
84
Info
Bits
84
Info
Bits
84
Info
Bits
84
Info
Bits
84
Info
Bits
84
Info
Bits
84
Info
Bits
C1
(0)
C1
(0)
C1
(0)
C1
(0)
C1
(0)
C1
(0)
C1
(0)
84
Info
Bits
84
Info
Bits
84
Info
Bits
84
Info
Bits
84
Info
Bits
84
Info
Bits
84
Info
Bits
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
15
- 1 for DS3 and STS-1 modes and 2
F2
(0)
F2
(0)
F2
(0)
F2
(0)
F2
(0)
F2
(0)
F2
(0)
(Table
84
Info
Bits
84
Info
Bits
84
Info
Bits
84
Info
Bits
84
Info
Bits
84
Info
Bits
84
Info
Bits
4-G), reports its status through the PRBS output pin (hardware
28 of 61
C2
(0)
C2
(0)
C2
(0)
C2
(0)
C2
(0)
C2
(0)
C2
(0)
84
Info
Bits
84
Info
Bits
84
Info
Bits
84
Info
Bits
84
Info
Bits
84
Info
Bits
84
Info
Bits
F3
(0)
F3
(0)
F3
(0)
F3
(0)
F3
(0)
F3
(0)
F3
(0)
23
84
Info
Bits
84
Info
Bits
84
Info
Bits
84
Info
Bits
84
Info
Bits
84
Info
Bits
84
Info
Bits
- 1 for E3 mode.
15
C3
(0)
C3
(0)
C3
(0)
C3
(0)
C3
(0)
C3
(0)
C3
(0)
- 1 (DS3 or STS-1) or 2
Table 4-F
84
Info
Bits
84
Info
Bits
84
Info
Bits
84
Info
Bits
84
Info
Bits
84
Info
Bits
84
Info
Bits
Figure 8-1
F4
(1)
F4
(1)
F4
(1)
F4
(1)
F4
(1)
F4
(1)
F4
(1)
shows, the PRBS
84
Info
Bits
84
Info
Bits
84
Info
Bits
84
Info
Bits
84
Info
Bits
84
Info
Bits
84
Info
Bits
and
Figure
23
- 1