DS3154 Maxim Integrated Products, DS3154 Datasheet - Page 24

• Manufacturer Part Number: DS3154
• Description: Network Controller & Processor ICs Quad DS3-E3-STS-1 Li ne Interface Unit ST
• Manufacturer: Maxim Integrated Products

Specifications of DS3154

• Product: Framer
• Number Of Transceivers: 4
• Data Rate: 51.840 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 400 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TE-CSBGA

When RLCV is asserted to flag a BPV, the RDAT pin outputs a one. The state bit that tracks the polarity of the last
BPV is toggled on every BPV, whether part of a valid B3ZS/HDB3 codeword or not.
To support a glueless interface to a variety of neighboring components, the polarity of RCLK can be inverted.
Normally, data is output on the RPOS/RDAT and RNEG/RLCV pins on the falling edge of RCLK. To output data on
these pins on the rising edge of RCLK, pull the RCINV pin high (hardware mode) or set the RCINV configuration bit
(CPU bus mode).
The RCLK, RPOS/RDAT, and RNEG/RLCV pins can be tri-stated to support protection switching and redundant-
LIU applications. This tri-stating capability supports system configurations where two or more LIUs are wire-ORed
together and a system processor selects one to be active. To tri-state RCLK, RPOS/RDAT, and RNEG/RLCV,
assert the RTS pin or the RTS configuration bit.
Receive Line-Code Violation Counter. The line-code violation counter is always enabled regardless of the
settings of the RBIN pin or the RBIN configuration bit. The receiver has an internal 16-bit saturating counter and a
16-bit latch, which the CPU can read as registers RCVH and RCVL. The value of the internal counter is latched into
the RCVH/RCVL register and cleared when the receive code-violation counter update bit, RCVUD, is changed from
a zero to a one. The RCVUD bit must be cleared back to a zero before a new update can occur. If there is an LCV
increment pulse and an update pulse in the same clock period, the counter is preset to a one rather than cleared
so that the LCV is not missed. The counter is incremented when the RLCV pin flags a code violation as described
in the Framer Interface Format and the B3ZS/HDB3 Decoder section. The counter saturates at 65,535 (0FFFFh)
and does not roll over.
Receiver Power-Down. To minimize power consumption when the receiver is not being used, assert the RPD
configuration bit (CPU bus mode). When the receiver is powered down, the RCLK, RPOS/RDAT, and RNEG/RLCV
pins are tri-stated. In addition, the RXP and RXN pins become high impedance.
Receiver Jitter Tolerance. The receiver exceeds the input jitter tolerance requirements of all applicable
telecommunication standards in
Figure 6-1. Receiver Jitter Tolerance
ITU bit set to 1
–
A BPV with the same polarity as the last BPV.
10
1.0
0.1
DS3 GR-499 Cat II
DS3 GR-499 Cat I
10
15
Table
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
30
STS-1 GR253
E3 G.823
1-A. See
100
10
5
Figure
300
1.5
24 of 61
FREQUENCY (Hz)
669
6-1.
1k
2.3k
10k
DS315x JITTER TOLERANCE
22.3k
60k
100k
0.3
0.15
0.1
300k
800k
1M