DS21354LB Maxim Integrated Products, DS21354LB Datasheet - Page 99
DS21354LB
Manufacturer Part Number
DS21354LB
Description
Network Controller & Processor ICs E1 Single-Chip Trans ceiver (SCT) E1 Fram
Manufacturer
Maxim Integrated Products
Datasheet
1.DS2154LNA2.pdf
(124 pages)
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Figure 17-1. IBO Basic Configuration Using Four SCTs
17.1.
In channel interleave mode data is output to the PCM data-out bus one channel at a time from each of the
connected SCTs until all channels of frame n from all each SCT has been place on the bus. This mode can
be used even when the connected SCTs are operating asynchronous to each other. The elastic stores will
manage slip conditions. See
17.2.
In frame-interleave mode, data is output to the PCM data-out bus one frame at a time from each of the
connected SCTs. This mode is used only when all connected SCTs are synchronous. In this mode, slip
conditions are not allowed. See
Channel Interleave
Frame Interleave
MASTER
SCT
SLAVE #1
CI
CO
CI
CO
RSYSCLK
TSYSCLK
RSYSCLK
TSYSCLK
TSSYNC
TSSYNC
RSYNC
RSYNC
TSER
RSER
TSER
RSER
RSIG
TSIG
RSIG
TSIG
Figure 18-11
Figure 18-2
and
and
Figure 18-5
Figure 18-6
99 of 124
SALVE #3
SLAVE #2
CI
CO
CI
CO
RSYSCLK
TSYSCLK
RSYSCLK
TSYSCLK
TSSYNC
TSSYNC
for details.
RSYNC
RSYNC
TSER
RSER
TSER
RSER
for details.
RSIG
TSIG
RSIG
TSIG
8.192MHz System Clock In
System 8KHz Frame Sync In
PCM Signaling Out
PCM Signaling In
PCM Data In
PCM Data Out
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